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ess technology, inc. sam0400-103101 1 preliminary es6008/18/28/38 vibratto tm dvd processor solutions data sheet description built on ess?s proprietary and flexible programmable multimedia processor architecture, the vibratto tm series of dvd processors combine audio/video stream data processing, system control and housekeeping functions, video postprocessing, and display format encoding, enabling various dvd-based multimedia electronics to be built with minimal external components. the vibratto series includes new features for dvd-audio support, progressive scan video output, and built-in tv encoder and video dacs. all of the vibratto dvd processors each include two parallel processing units, a risc processor, a vector engine, and supplemental hardware resources for implementing specialized encoding and decoding tasks in the device architectures. all of these resources are interconnected with two separate data buses, each with its own dma unit and interface to external memory. the processing units enable simultaneous parallel execution of system commands and data processing. both the risc processor and vector engine are independently programmable. each has its own on-chip cache memory. the risc processor and its associated hardware units perform bit stream parsing, control audio data output, transfer video and audio data to the vector engine and service system control and housekeeping functions. the vector engine and associated hardware units perform audio and video microcode processing required by a/v standards such as dolby digital tm , dts tm , mpeg and jpeg. these processing tasks include audio dsp, video motion compensation and estimation, loop filtering, discrete cosine transforms (dct) and inverse dct, quantization and inverse quantization. the vibratto dvd processors support both jpeg/mp3 audio playback and the kodak picturecd jpeg display format. these new features allow picture cds created with images and voiceovers from digital cameras to be enjoyed in a dvd player or home theater system. all of the vibratto dvd processors support both parallel and serial dvd loader interfaces for system mpeg a/v data stream input, industry standard-i 2 s bus for audio data input and output, direct system eprom and sdram access for high-speed command fetching and audio/video data buffering and processing. the vibratto dvd processors are available in 208-pin plastic quad flat pack (pqfp) device packages. features ? dedicated core and i/o power supplies for low-power operation; integrated 32-bit risc processor for system host, eliminating requirements of an external host cpu supports dvd-video, dvd-audio, videocd 1.1, 2.0, and 3.0, super videocd (svcd), cd-da, mp3, and kodak picture-cd supports parallel and serial interfaces to atapi, compact flash, dci, ide and udf dvd loaders direct interface of 8- or 16-bit sdram of up to 128-mb capacity at a variety of speed grades direct interface of up to 4 banks of 8- or 16-bit eprom or flash eprom; automatic firmware updating of flash eprom through dvd loader video built-in ntsc/pal encoder includes field-adaptive de- interlacing for progressive scan video output for clearer and more stable display (es6028 and es6038 only) macrovision 7.1 and macrovision agc 1.03 compliant video outputs for 480-pixel progressive scan and for ntsc/pal interlaced video four built-in 10-bit video dacs provide simultaneous video outputs of composite and s-video, or composite and yuv; supports selectable 8-bit ccir 601 4:2:2 yuv outputs 8-bit on-screen display (osd) controller with 3-bit blending provides display with 256 colors in 8 degrees of transparency on-chip subpicture unit (spu) decoder supports karaoke lyric, subtitles, and eia-608 compliant line 21 captioning video error concealment, motion zoom and pan and ntsc to pal and pal to ntsc conversion supported audio dolby digital (ac-3), dvd-audio, pro logic, dts, mpeg-1 layer 2 and 3 audio (mp3), and high-definition compatible digital ? (hdcd) decoding on-chip dolby digital (ac-3) and dts 5.1 channel decoding and output (ES6018/28/38 only) dolby digital and dts s/pdif digital audio output. dolby digital class a, dts, and hdcd certified meridian lossless packing ? (mlp) decoding and linear pcm for dvd-audio (es6038 only)
2 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet contents preliminary contents system block diagram ......................................... 5 es60x8 pinout diagram ....................................... 6 es60x8 pin description ........................................ 7 licensing requirements...................................... 11 dolby digital licensing ................................. 11 macrovision licensing .................................. 11 functional description ........................................ 12 vibratto device architecture ......................... 12 ess risc processor ................................. 12 instruction cache ...................................... 13 data cache ............................................... 13 risc interrupts ......................................... 13 command queue and video processor .... 14 command queue ...................................... 14 video processor ........................................ 14 dma controller ........................................... 14 transport .................................................... 14 private bus dma interface.......................... 15 pribus arbiter state machine ...................... 15 crt controller ........................................... 15 video decoder ........................................... 15 block mode ............................................... 16 step mode ................................................. 16 video encoder .............................................. 16 on-screen display (osd) controller ........... 16 subpicture unit (spu) decoder ................... 17 spu video data framing .......................... 17 coding and media content protection ......... 17 ntsc closed captioning ........................... 17 pal teletext captioning ............................ 19 cppm, css-2, and macrovision ................ 19 ac-3 audio decoding (ntsc) ................... 19 ac-3 encoding (ntsc) .............................. 20 dts multi-channel decoding ..................... 20 dvd-audio (es6038 only) and mlp decoding ........................................ 20 mlp decoding .......................................... 20 mlp encoding ........................................... 20 hdcd decoding and filtering .................... 20 progressive scan (es6028 and es6038 only) ......................................... 21 video error concealment ........................... 21 disk error concealment ............................. 21 device interfaces .......................................... 21 audio interface ........................................... 21 dvd loader interfaces ............................... 21 host interface ............................................. 23 system sram interface ............................. 23 tdm interface ............................................. 24 tdm operation and bit settings ............... 24 vacuum fluorescent display (vfd) control interface ..................................... 25 video memory interface ............................... 25 sdram considerations ............................. 25 sdram address mapping ......................... 25 sdram configuration requirements.......... 25 video interface .............................................26 video display output .................................. 26 video bus ................................................... 26 safe caption area ...................................... 26 video post-processing ............................... 27 video timing .............................................. 27 registers ............................................................ 28 host interface (host side) registers ............28 video interface registers .............................29 video output registers .............................. 29 on screen display (osd) controller registers ................................................. 33 subpicture unit (spu) decoder registers ................................................. 34 spu contrast index registers ................... 37 spu color index registers ........................ 37 host interface (risc side) registers ...........38 host interface (risc-sram interface) registers ................................40 bus controller (video processor) registers .................................................41 bus controller (memory controller) registers .................................................42 bus controller (command queue) registers .................................................43 audio interface registers .............................43 s/pdif interface registers ......................... 45 tdm interface registers ...............................45 sdram read and write timing diagrams ........47 sram interface timing ......................................52 tdm interface timing .........................................54 host interface timing .........................................55 dci timing ..........................................................57 audio transmit and receive timing diagrams ..........................................................58 video timing diagrams ......................................60 electrical specifications ......................................66 absolute maximum ratings ..........................66 recommended operating conditions ..........66 dc electrical characteristics ....................... 66 video dac ................................................. 66 ac electrical characteristics ........................67
ess technology, inc. sam0400-103101 3 es6008/18/28/38 data sheet figures preliminary es60x8 design guide........................................ 68 dvd printed circuit board layout guidelines .............................................. 68 about multilayer boards ..............................68 power and ground planes ..........................68 digital signal interconnect ..........................68 analog signal interconnect .........................68 layout considerations ................................68 power supply decoupling ...........................68 compensation capacitor decoupling .........69 reference voltage decoupling ...................69 dac current adjustment resistor ..............69 sdram signal routing ...............................69 about the vibratto evaluation board ........... 69 evaluation mainboard features ..................69 connector pin assignments ......................... 70 memory interface ........................................72 reset ...........................................................72 external sram/flash ..................................72 audio pll ....................................................72 audio input...................................................72 video, vfd and s/pdif .............................. 72 about the dvd-audio daughterboard ......... 73 daughterboard features ............................ 73 functional description ................................ 73 jumpers ..................................................... 74 connector pin assignments ....................... 74 appendix a: mainboard reference design schematics .......................................... 76 appendix b: mainboard bill of materials ............ 80 appendix c: mainboard gerber files ................. 82 appendix d: dvd-audio daughterboard schematics ...................................................... 91 appendix e: dvd-audio daughterboard bill of materials ................................................. 97 appendix f: dvd-audio daughterboard gerber files ..................................................... 99 appendix g: vfd bill of materials ................... 106 appendix h: vfd gerber files......................... 108 appendix i: vfd control panel schematics..... 115 mechanical dimensions ................................... 118 ordering information ........................................ 120 figures figure 1 vibratto system block diagram ...... 5 figure 2 es6008/18/28/38 pinout ................. 6 figure 3 vibratto block diagram ................. 12 figure 4 ess risc block diagram ............. 13 figure 5 private bus dma block diagram ... 15 figure 6 typical subpicture data framing format ........................................ 17 figure 7 typical ac-3 sync audio framing ...................................... 19 figure 8 video output timing ..................... 26 figure 9 safe caption area ......................... 26 figure 10 video post-processing .................. 27 figure 11 8-bit yuv input timing .................. 27 figure 12 horizontal video timing ................ 27 figure 13 vertical video timing .................... 27 figure 14 sdram random column read timing ............................... 47 figure 15 sdram random column write timing ............................... 48 figure 16 sdram random row read timing ............................... 49 figure 17 sdram random row write timing ............................... 50 figure 18 sram read timing ...................... 52 figure 19 sram write timing ...................... 53 figure 20 tdm interface timing .................... 54 figure 21 host bus read timing .................. 55 figure 22 host bus write timing .................. 56 figure 23 dci interface timing ..................... 57 figure 24 right justified mode / 16-bit cycle frame / 16-bit data frame ......... 58 figure 25 right justified mode / 24-bit data frame / first-bit sent first / msb first .................................... 58 figure 26 right justified mode / 32-bit cycle frame / 24-bit data frame / last bit sent last / lsb first .............. 58 figure 27 left justified mode / 32-bit cycle frame / 32-bit data frame / msb first ............................................. 59 figure 28 i 2 s mode......................................... 59 figure 29 ntsc timing ................................. 60 figure 30 pal timing .................................... 60 figure 31 ntsc closed captioning timing ......................................... 61 figure 32 pal teletext / vertical blanking interval timing ............................ 61 figure 33 line 21 preamble address codes (same as fcc part 15.119) ....... 62
4 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet tables preliminary figure 34 ntsc composite (vdac) line output waveform ........................ 63 figure 35 pal composite (vdac) line output waveform ........................ 63 figure 36 luma (ydac) line output waveform ................................... 64 figure 37 chroma (cdac) line output waveform ................................... 64 figure 38 sync and pixel clock timings ....... 65 figure 39 pixel, doubled pixel, tdm and audio master clock timing ......... 67 figure 40 pcb layout considerations .......... 68 figure 41 typical video dac connection diagram ....................................... 69 figure 42 high-pass and low-pass filter configurations .................... 73 figure 43 daughterboard block diagram ...... 74 figure 44 daughterboard connectors ........... 74 figure 45 es60x8 device interface ............... 76 figure 46 memory interface .......................... 77 figure 47 atapi interface ............................. 78 figure 48 video and audio dacs ................. 79 figure 49 component layer .......................... 82 figure 50 solder layer .................................. 83 figure 51 drill template ................................ 84 figure 52 ground plane ................................ 85 figure 53 power layer .................................. 86 figure 54 solder mask top layer ................. 87 figure 55 solder mask bottom layer ............ 88 figure 56 silkscreen bottom layer ............... 89 figure 57 silkscreen top layer .................... 90 figure 58 audio and control interface .......... 91 figure 59 video connectors .......................... 92 figure 60 karaoke and audio dacs ............. 93 figure 61 fl and fr filters ...........................94 figure 62 c, ls and rs filters ......................95 figure 63 lfe filter and cd-da amplifier ....96 figure 64 daughterboard silkscreen .............99 figure 65 daughterboard top layer ...........100 figure 66 daughterboard bottom layer ......101 figure 67 daughterboard solder mask top layer ..................................102 figure 68 daughterboard solder mask bottom layer .............................103 figure 69 daughterboard solder paste top layer ..................................104 figure 70 daughterboard drill hole template ...................................105 figure 71 vfd control panel top layer ..................................108 figure 72 vfd control panel bottom layer .............................109 figure 73 vfd control panel drill template ...................................110 figure 74 vfd control panel solder mask bottom layer .............................111 figure 75 vfd control panel solder mask top layer ..................................112 figure 76 vfd control panel solder paste layer ...............................113 figure 77 vfd control panel silkscreen layer .........................................114 figure 78 vfd preamp.................................115 figure 79 vfd control panel switching interface.....................116 figure 80 vfd controller interface...............117 figure 81 208-pin plastic quad flat package (pqfp) .......................118 tables table 1 es6008/18/28/38 pin description ... 7 table 2 vibratto instruction and data cache attributes ......................... 13 table 3 ess risc interrupts ..................... 13 table 4 private bus dma devices .............. 15 table 5 private bus dma ports .................. 15 table 6 line 21 standard character set .............................................. 17 table 7 line 21 special character set ...... 19 table 8 video error concealment modes ......................................... 21 table 9 packet commands for atapi c/dvd devices ........................... 22 table 10 cf-ata command set .................22 table 11 udf entity identifier defintions .....23 table 12 typical sdram configurations..... 25 table 13 sdram configurations and signal pins ...........................26 table 14 safe caption area dimensions .....26 table 15 ess risc clock relationship to pixel clocks ................................27 table 16 sdram interface timing ...............51 table 17 operating ac characteristics ........51 table 18 dc electrical characteristics .........66 table 19 clock timing parameters ..............67
ess technology, inc. sam0400-103101 5 es6008/18/28/38 data sheet system block diagram preliminary table 20 add-on dvd player boards and modules ............................... 69 table 21 the vibratto clock frequency matrix .......................................... 70 table 22 video output combinations matrix .......................................... 70 table 23 js1 dvd drive expansion connector ................................... 70 table 24 js2 atapi interface connector .... 70 table 25 js3 video connector .................... 70 table 26 js4 power connector ................... 71 table 27 js5 vfd interface connector ....... 71 table 28 js6 s/pdif connector .................. 71 table 29 js7 audio input connector ........... 71 table 30 js8 audio output connector ........ 71 table 31 js9 audio board connector ......... 71 table 32 js10 sram interface connector .. 71 table 33 js11 eprom/rom emulator1 interface connector .................... 72 table 34 u8 audio pll sampling frequencies ................................. 72 table 35 jp1 jumper settings ..................... 74 table 36 js1 mic input ............................... 74 table 37 js2 dvd decoder interface .......... 75 table 38 js4 s/pdif input interface ........... 75 table 39 js5 reset/powerdown .................. 75 table 40 js6 daughterboard power connector ................................... 75 table 41 js7 coax modulator output .......... 75 table 42 js8 video input ............................. 75 table 43 mainboard bill of materials ............ 80 table 44 dvd-audio daughterboard bill of materials ........................... 97 table 45 vfd bill of materials .................... 106 system block diagram figure 1 vibratto system block diagram vibratto 8 mb sdram dvd drive rom/flash vfd driver 5.1 audio dac tv speakers or vfd panel video audio eeprom atapi compact flash dci tvm ude vstem s/pdif out or dts audio a/v receiver
6 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet es60x8 pinout diagram preliminary es60x8 pinout diagram the identical device pinouts for the es6008, ES6018, es6028 and es6038 are shown in figure 2. figure 2 es60x8 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 lcs1# loe# ld0 vss lcs3# lcs2# aux[0] la21 la20 reset# vee tsd3 hiocs16#/camclk/aux3[4] ha1/aux4[3] vss ha0/aux4[2] hwr#/dci_clk/aux4[5] hrd#/dci_ack#/aux4[6] hd4/dci4/aux1[4] hd5/dci5/aux1[5] hd6/dci6/aux1[6]/vfd_dout hd2/dci2/aux1[2] hd3/dci3/aux1[3] vee vcc db8 vcc db5 db9 dcs0# vcc vss tsd0/sel_pll0 tsd1/sel_pll1 tdmfs tdmclk tdmdr tdmtsc# tws/sel_pll2 vee la4 la5 la6 la7 la8 la9 vss vcc la10 la11 la12 la13 la14 la15 la16 vss vee la17 la18 la19 tdmdx/rsel vss tsd2 spdif/pll3 nc vss mclk tbck vee vee vss vss dqm rsd rws rbck nc xin xout avee dsck vss db15 db13 db11 db1 vss dmbs1 dras# doe#/dsck_en vee dma9 dma7 vss dma5 dma3 vee dcs1# db14 db12 db10 db0 vee dmbs0 dwe# dcas# vss dma8 dma6 vee dma4 dma2 vss db7 db6 vss db4 db3 db2 dma11 dma10 dma1 dma0 hcs3fx#/aux3[6] hcs1fx#/aux3[7] vss hiordy/aux3[3] vss hd13/aux2[5]/sp hd12/aux2[4]/c2po hd11/aux2[3]//irq hd10/aux2[2]/sqsk hd9/aux2[1]/sqso hd8/dci_fds#/aux2[0]/vfd_clk vss hirq/dci_err#/aux4[7] hrst#/aux3[5] hrrq#/aux4[0] hwrq#/dci_req#/aux4[1] hd15/aux2[7]/ir hd14/aux2[6]/sqsi vcc hd7/dci7/aux1[7]/vfd_din hd1/dci1/aux1[1] hd0/dci0/aux1[0] vcc vss hsync#/camin7/aux3[0] pclk2xscn/camin4 yuv7/camin3 yuv6/vdac pclkqscn/camin5/aux3[2] vsync#/camin6/aux3[1] yuv5/ydac vss advee yuv4/rset yuv3/comp yuv2/cdac yuv1/vref yuv0/camin2/udac dclk vee aux[7] aux[6] vee ld1 ld2 la3 ld12 vee ha2 /aux4[4] vee vee ld3 ld5 ld9 ld13 lwrhl# camin1 aux[1] aux[3]/ior# ld4 ld6 ld10 ld14 vss la0 aux[2]/iow# aux[4] vee ld7 ld11 ld15 vee la1 vss aux[5] vss ld8 vss lwrll# camin0 la2 vss vcc lcs0# vss 208-pin pqfp package es6008/18/28/38
ess technology, inc. sam0400-103101 7 es6008/18/28/38 data sheet es60x8 pin description preliminary es60x8 pin description table 1 lists the identical pin descriptions for the es6008, ES6018, es6028 and es6038. table 1 es60x8 pin description name number i/o definition vee 1,18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 i i/o power supply. vss 8, 17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98, 103, 112, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 i ground. la[21:0] 23:19, 16:10, 7:2, 207:204 o device address output. vcc 9, 35, 44, 83, 121, 139, 172 i core power supply. reset# 24 i reset input, active low. tdmdx 25 o tdm transmit data. rsel i rom select. tdmdr 28 i tdm receive data. tdmclk 29 i tdm clock input. tdmfs 30 i tdm frame sync. tdmtsc# 31 o tdm output enable. tws 32 o audio transmit frame sync. sel_pll2 i system and dsck output clock frequency selection is made at the rising edge of reset#. the matrix below lists the available clock frequencies and their respective pll bit settings. tsd0 33 o audio transmit serial data port 0. sel_pll0 i refer to the description and matrix for sel_pll2 pin 32. tsd1 36 o audio transmit serial data port 1. sel_pll1 i refer to the description and matrix for sel_pll2 pin 32. tsd[2] 37 o audio transmit serial data output 2. tsd[3] 38 o audio transmit serial data output 3. rsel selection 016-bit rom 1 8-bit rom sel_pll2 sel_pll1 sel_pll0 clock type 0 0 0 vco off. 0 0 1 dclk 0 1 0 bypass mode 0 1 1 dclk x 2 1 0 0 dclk x 4.5 1 0 1 dclk x 3 1 1 0 dclk x 3.5z 1 1 1 dclk x 4
8 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet es60x8 pin description preliminary name number i/o definition mclk 39 i/o audio master clock for audio dac. tbck 40 o audio transmit bit clock. spdif 41 o s/pdif output. sel_pll3 i clock source select. nc 42, 48 no connect pins. leave open. rsd 45 i audio receive serial data. rws 46 i audio receive frame sync. rbck 47 i audio receive bit clock. xin 49 i crystal input. xout 50 o crystal output. avee 51 i analog power for pll. dma[11:0] 66:61, 58:53 o dram address bus [11:0]. dcas# 69 o dram column address strobe. doe# 70 o dram output enable. dsck_en o dram clock enable. dwe# 71 o dram write enable. dras# 72 o dram row address strobe. dmbs0 73 o sdram bank select 0. dmbs1 74 o sdram bank select 1. db[15:0] 96:93, 90:85, 82:77 i/o dram data bus [15:0]. dcs[1:0]# 97,100 o sdram chip select [1:0]. dqm 101 o data input/output mask. dsck 102 o output clock to sdram. dclk 105 i 27 mhz clock input to pll. yuv0 106 o yuv0 pixel output data. camin2 i camera input 2. udac o video dac output. y: luma component for yuv and y/c processing. c: chrominance signal for y/c processing. u: chrominance component signal for yuv mode. v: chrominance component signal for yuv mode. table 1 es60x8 pin description (continued) sel_pll3 clock source 0 crystal oscillator 1 dclk input mode ydac udac vdac cdac a y c composite c b y composite composite c c y u composite v dy u cv
ess technology, inc. sam0400-103101 9 es6008/18/28/38 data sheet es60x8 pin description preliminary name number i/o definition yuv1 107 o yuv1 pixel output data. vref i internal voltage reference to video dac. bypass to ground with 0.1 f capacitor. yuv2 108 o yuv2 pixel output data. cdac o video dac output. refer to description and matrix for udac pin 106. yuv3 109 o yuv3 pixel output data. comp i compensation input. bypass to advee with 0.1 f capacitor. yuv4 110 o yuv4 pixel output data. rset i dac current adjustment resistor input. advee 111 i analog power for video dac. yuv5 113 o yuv5 pixel output data. ydac o video dac output. refer to description and matrix for udac pin 106. yuv6 114 o yuv6 pixel output data. vdac o video dac output. refer to description and matrix for udac pin 106. yuv7 115 o yuv7 pixel output data. camin3 i camera yuv 3. pclk2xscn 116 i/o 27-mhz video output pixel clock. camin4 i camera yuv 4. pclkqscn 117 o 13.5-mhz video output pixel clock. camin5 i camera yuv 5. vsync# 118 i/o vertical sync, active low. camin6 i camera yuv 6. hsync# 119 i/o horizontal sync, active low. camin7 i camera yuv 7. hd[5:0] 127:122 i/o host data i/o [5:0]. dci[5:0] i/o dvd channel data i/o [5:0]. aux1[5:0] i/o aux1 data i/o [5:0]. hd[6] 128 i/o host data i/o [6]. dci[6] i/o dvd channel data i/o [6]. aux1[6] i/o aux1 data i/o [6]. vfd_dout i vfd data output. hd[7] 131 i/o host data i/o [7]. dci[7] i/o dvd channel data i/o [7]. aux1[7] i/o aux1 data i/o [7:0]. vfd_din i vfd data input. hd[8] 132 i/o host data bus 8. dci_fds# i/o dvd input sector start. aux2[0] i/o aux2 data i/o 0. vfd_clk i vfd clock input. hd[9] 133 i/o host data bus line 9. aux2[1] i/o aux2 data i/o [1] when selected. sqsq i subcode-q data. hd[10] 134 i/o host data bus line10. aux2[2] i/o aux2 data i/o [2] when selected. sqsk i subcode-q clock. table 1 es60x8 pin description (continued)
10 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet es60x8 pin description preliminary name number i/o definition hd[11] 135 i/o host data bus line11. aux2[3] i/o aux2 data i/o [3] when selected. irq o irq output. hd[12] 136 i/o host data bus line12. aux2[4] i/o aux2 data i/o [4] when selected. c2po i c2po error correction flag from cd-rom. hd[13] 137 i/o host data bus line13. aux2[5] i/o aux2 data i/o [5] when selected. sp i 16550 uart serial port input. hd[14] 140 i/o host data bus line14. aux2[6] i/o aux2 data i/o [6] when selected. sqsi i subcode-q sync. hd[15] 141 i/o host data bus line15. aux2[7] i/o aux2 data i/o [7] when selected. ir i ir remote control input. hwrq# 142 o host write request. dci_req# o dvd control interface request. aux4[1] i/o aux4 data i/o 1. hrrq# 143 o host read request. aux4[0] i/o aux4 data i/o 0. hirq 144 i/o host interrupt. dci_err# i/o dvd channel data error. aux4[7] i/o aux4 data i/o 7. hrst# 145 o host reset. aux3[5] i/o aux3 data i/o 5. hiordy 146 i host i/o ready. aux3[3] i/o aux3 data i/o 3. hwr# 149 i/o host write. dci_clk i/o dvd channel data clock. aux4[5] i/o aux4 data i/o 5. hrd# 150 ohost read. dci_ack# o dvd channel data valid. aux4[6] i/o aux4 data i/o 6. hiocs16# 151 i device 16-bit data transfer. camclk i camera port pixel clock input. aux3[4] i/o aux3 data i/o 4. hcs1fx# 152 o host select 1. aux3[7] i/o aux3 data i/o 7. hcs3fx# 153 o host select 3. aux3[6] i/o aux3 data i/o 6. ha[2:0] 158, 155:154 i/o host address bus. aux4[4:2] i/o aux4 data i/os [4:2]. aux[1:0] 160 i/o auxiliary ports 1:0. table 1 es60x8 pin description (continued)
ess technology, inc. sam0400-103101 11 es6008/18/28/38 data sheet licensing requirements preliminary licensing requirements dolby digital licensing dolby digital audio enabling software is provided with the vibratto series of dvd processors. dolby is a trademark of the dolby laboratories. supply of this implementation of dolby technology does not convey a license or imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use this implementation in any end-user or ready-to-use final product. companies planning to use this implementation in products must obtain a license from dolby laboratories licensing corporation before designing such products. additional per-chip royalties may be required and are to be paid by the purchaser to dolby laboratories, inc. details of the oem dolby digital license may be obtained by writing to: dolby laboratories inc. dolby laboratories licensing corporation attn.: intellectual property manager 100 potrero avenue san francisco, ca 94103-4813 macrovision licensing macrovision copy protection is supported in the vibratto series of dvd processors. the use of macrovision ? s copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. a valid macrovision license must be in effect between the vibratto purchaser and macrovision corporation. additional per- chip royalties may be required and are to be paid by the purchaser to macrovision corporation. details of the macrovision license may be obtained by writing to: macrovision corporation 1341 orleans avenue sunnyvale, ca 94089 name number i/o definition aux[2] 162 i/o auxiliary port 2. iow# o i/o write strobe. aux[3] 165 i/o auxiliary port 3. ior# o i/o read strobe. aux[7:3] 169:166 i/o auxiliary ports 7:3. loe# 170 o device output enable. lcs[3:0]# 176:173 o chip select [3:0]. ld[15:0] 197:194, 191:185, 182:178 i/o eprom device data bus. lwrll# 198 o device low-byte write enable. lwrhl# 199 o device high-byte write enable. camin0 202 i camera yuv 0. camin1 203 i camera yuv 1. table 1 es60x8 pin description (continued)
12 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary functional description figure 3 shows the internal block diagram for the basic vibratto dvd processor. figure 3 vibratto block diagram vibratto device architecture the vibratto device architecture includes a risc processor, crt controller, transport mechanism, video encoder, memory controller, on-screen display (osd) controller and video processor. ess risc processor embedded in the vibratto is a 32-bit data pipelined risc processor, with a combined 16 kb instruction and data cache subsystem. programming of the risc processor is done mostly in c. for applications involving an external host processor the communication between a host processor and the vibratto is handled by a host interface module. the host interface can also be used for high speed data input and output. the ess risc processor instruction and data cache subsystem is organized as a two-way set associative. on a cache load-miss and write-miss, the cache lines are allocated into the cache memory. aux[7:0] hsync# pclk2xscn pclkqscn reset# vsync# xin xout clock mpeg decoder on screen video video output processor host/atapi/udf serial audio processor display loader interface interface serial audio interface tdm interface dram screen display clock, processor interface host/atapi udf yuv[7:0] ess risc dram interface loe# la[21:0] ld[15:0] lcs#[3:0] lwrhl# lwrll# hiordy hcs[1,3]fx# ha[2:0] hiocs16# hwr# hd[15:0] hrdq# hwrq# hirq# hrst# rsd rws rbck spdif tbck mclk tsd[3:0] tws tdmclk tdmdr tdmdx tdmfs tdmtsc# dsck_en dqm dcs#[1:0] dma[11:0] dwe# doe# dras#[2:0] db[i5:0] registers dcas# dsck hrd# tdm interface system dvd descramble 2kx32 rom 512x32 sram dci loader interface dci interface dci_ack# dci_clk dci_req# dci_err# dci_fds# dci[7:0] dma controller demultiplexer sub-picture decoder interface sram interface video encoder aux ports and reset cdac ydac udac vdac vref comp rset
ess technology, inc. sam0400-103101 13 es6008/18/28/38 data sheet functional description preliminary before cache line operation, the writeback operation may be performed if the cache content and main memory contents are different. the ess risc also performs all power management and system configuration functions for the vibratto, as shown in the block diagram in figure 4. figure 4 ess risc block diagram the programmable multimedia processor (pmp) core includes the proprietary single instruction, multiple data (simd) dsp, which can handle four 16-bit-wide data streams. also included in the device architecture are a screen display controller, a digital video encoder with four dacs, a video input block, video system interfaces, fifos and dma controllers. the pmp core resource can be accessed only from the ess risc core. together, the ess risc and the pmp cores form ess technology ? s field-proven pmp engine. instruction cache the instruction cache of the risc core is an on-chip memory array configured to a size of 8 kb. the cache is virtually indexed and physically tagged, allowing the virtual-to-physical address translation to occur in parallel with the cache access rather than having to wait for the physical address translation. data cache the data cache of the risc core is an on-chip memory array configured to a size of 8 kb. like the instruction cache, the data cache is also virtually indexed and physically tagged and handles the virtual-to-physical address translation process the same way as the instruction cache. table 2 lists the attributes for both the instruction and data caches of the vibratto. table 2 vibratto instruction and data cache attributes risc interrupts twelve events can cause interrupts to the ess risc. each event has a status bit to indicate the occurrence of the event and an enable bit to mask it from interrupting the ess risc. table 3 lists all of the ess risc interrupts and the conditions that cause them. multiplier/ divider unit execution unit instruction cache data cache (writeback) cache control memory interface pwr mgmt timers to l o c a l intdbus size set associativity line size write policy instruction cache 8 kb two-way set associative 16 bytes n/a data cache 8 kb two-way set associative 16 bytes writeback table 3 ess risc interrupts interrupt group caused by condition how to clear video irq 0 video line number equals value in?videoirq?register risc eprom and sram wait states timer 0 timer register wraps from 3ffffh to 00000h writing?1? to ?clrirq? register bit 3 bcdw 0 dma bus controller data is waiting to be read after dbus- read command reading the?rlatchl? register cmd empty 0 dma bus controller com- mand queue goes empty writing a command to ?cmdque? h en idle 1 huffman encoder state machine goes idle writing ?1? to ?clrirq? register bit 2 h de idle 1 huffman decoder state machine goes idle writing ?1? to ?clrirq? register bit 1 data transfer 1 either host-to-risc data tre or risc-to-host dw (host can select) tre cleared when risc reads data; dw cleared when risc writes data block done 1 after dma controller has read six blocks of rlas from vp to dram write any data to ?clrhmade? register cmd half- empty 2 dma bus controller com- mand queue is less than or equal to half full write commands to ?cmdque? so queue becomes over half full debug 2 debugirq pin goes high debugirq pin goes low fifo level 2 either encoder output fifo or decoder input fifo reach certain fullness writing ?1? to bit 8 of ?mipctlreg? register host to risc 2 host sets host-to-risc inter- rupt bit 7 of ?hostcontrol0? reg- ister (host address 2) writing?1? to bit 0 of?mipctlreg? register
14 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary command queue and video processor command queue the command queue module controls the video processor module of the risc engine. the command queue allows the risc to be decoupled from the video processor module by building a command list of instructions used to control its operation. the command list includes instructions for handling video processor dma, data transfers, send and receive instructions, and waits to receive the current status of the video processor. the depth of the command queue is approximately 64 entries. when the command queue is setting up dmas for the video processor, the command queue automatically writes to dma channel 0 of the bus controller. the buscon_cmdque_vpdmasetup register at index 0x20008200h accepts the video processor dma access requests being routed to the command queue and prioritizes them in the respective order received. the incoming commands are always executed in the order they are written to the queue by the risc. both requests for 7-bit vales of delta-y longwords (dely[6:0]) and 9-bit values of delta-x scan lines (delx[8:0]) are processed. the buscon_cmdque_vpdmaaddr register at index 0x2000820ch stores the dma addresses of the incoming commands so that the command can be decoded when execution takes place. the buscon_cmdque_status register at index 0x20008224h constantly monitors the status of the command queue. the command queue of the vibratto receives its dma inputs from two of the three key bus controller registers. video processor the video processor consists of a programmable simd engine and 2 kb of internal cache memory. the video processor module performs instruction processing for four types of instructions: memory instructions conditional branch instructions compute instructions, and compute immediate instructions. the video processor executes macroblock level tasks such as predictive coding, motion estimation, and motion compensation. the video processor can also be used for a wide range of time-critical signal processing tasks, including dolby digital (ac-3) audio decoding and both video pre- processing and post-processing. the video processor enables the vibratto to perform arbitrary vertical filtering and scaling of outgoing video. the video processor is controlled by 32-bit and 16-bit wide dual issue micro-instructions. commonly used microcode subroutines are stored in 8 kb of internal microcode rom, while less frequently used microcode segments can be downloaded on demand to 2 kb of internal microcode ram. dma controller the dma bus controller is controlled by the video processor and controls multiple dma channels for the transfer of 32-bit data between: video data bus and memory video decoder and memory ess risc and memory, and ess risc and video data bus. writes from the ess risc to the video processor command bus are also performed by the dma bus controller, along with waits on status readback from the video processor status bus. a separate dma channel is used for memory refresh. to improve memory bandwidth utilization, internal gateway fifos are used extensively. the dma controller includes two registers in the device architecture that interface directly to the video processor. the buscon_vp_control register at index 0x20008000h performs all video processor microcode loading and reset. the buscon_vp_stat register at index 0x20008004h provides the status of the internal command queue of the video processor while monitoring the status of all sequencing, data transfers and i/o states. transport the vibratto incorporates a micro-programmable system demultiplexer capable of handling mpeg-1 system stream, mpeg-2 program stream, mpeg-2 transport stream, and other proprietary system multiplexes. the transport mechanism contains a 32-entry packet id table and satisfies the transport requirements of the dvb standard. the transport mechanism performs parsing of all packetized elementary streams (pess) and selects the destinations for all of the audio and video elements in a given bit stream for processing by the ess risc engine. each bit stream has a packet id (pid) table, which includes a 4-bit destination field. the transport mechanism determines the destination of the elements so that the ess risc engine knows where to send the final data output after processing. after processing, the transport mechanism also performs data flushing of all the buffer fifos in the device.
ess technology, inc. sam0400-103101 15 es6008/18/28/38 data sheet functional description preliminary private dma bus interface the private dma bus interface of the vibratto sets the priorities for handling data transfers. the vibratto makes data transfers between the tdm interface the highest priority because devices connected to these interfaces, such as cd-rom drives and dvd loaders, typically require specific timing for data transfers. both cd-rom drives and dvd loaders use the tdm interface as the physical path for data transfers between the drive/loader mechanism and the memory interface of the vibratto. data transfers have intermediate priority because the resources that perform these data transfers are both internal to the vibratto and have flexible timing requirements. data transfers involving the host interface have the lowest priority in the vibratto because host devices coupled to the host interface can be stalled if the data is not ready when requested. the data bus dma is managed by the bus controller, while the pribus dma is managed by the transport mechanism. the pribus dma devices are listed in table 4. table 4 private bus dma devices the private bus dma ports are listed in table 5. table 5 private dma bus ports the private bus dma block diagram is depicted in figure 5. figure 5 private bus dma block diagram private bus dma arbiter state machine the vibratto includes a private bus dma arbiter state machine. this state machine controls the read and write accesses to and from pribus for all the devices within the vibratto. the state machine receives all data waiting (dw) and transfer register empty (tre) signals from the devices, and implements a round-robin dispatching scheme to drive enables to all the devices in the vibratto. each of the four transport channels (video, audio, aux1 and aux2) will have a maximum latency of four clk80 cycles. the maximum latency for all other transport channels are 16 clk80 cycles each. crt controller the video output timing of the vibratto is controlled by a pixel clock and the horizontal and vertical sync signals. pixels are clocked out of the vibratto by the pixel clock. the sync signals determine when the active video data is transferred. the timing of the active video and sync signals is determined by the crt controller inside the vibratto. the output timing can either be internally generated, or slaved to another video sync source. video decoder the vibratto decoder module performs both mpeg-1 and mpeg-2 decoding and parsing. a high-speed engine decodes mpeg variable length codes (vlc), using built- in mpeg-1 and mpeg-2 vlc tables. a programmable ram-based table controls automatic switching from one vlc table to the next. device type application or direction host dram to host decoder audio decoder video decoder audio audio to dram (audio out) dram to audio (audio in) video video to dram (video out) dram to video (video in) tdm dram to tdm transport 1 video bit stream to dram transport 2 audio bit stream to dram transport 3 aux1 to dram transport 4 aux2 to dram gate number application or direction gate 1 transport 1 gate 2 transport 2 gate 3 transport 3 gate 4 transport 4/audio to dram gate 5 audio decoder gate 6 video decoder gate 7 dram to audio gate 8 dram to tdm/dram to host host, audio, and video transfer inputs register tdm and transport 1:4 transfer inputs register gateway 1:8 transfer inputs register arbiter channel select counter enables timing private to host, audio, video writes and audio reads private to tdm, and transport 1:4 writes private to 1:4 writes 5:8 reads gateway and gateway
16 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary the programmable table is primarily intended to allow jpeg images with custom huffman tables to be decoded, but it also allows nonstandard codings to be decoded. the programmable table is also especially useful for h.261- compliant algorithms. not only can h.261-based temporal coefficient (tcoeff) tokens be decoded via the programmable table of the vibratto, but so can coded block pattern (cbp) tokens and motion vector tokens. during decoding, the ess risc reads the incoming bitstream. the ess risc software determines the size and meaning of the token it is parsing and then discard the number of bits of the token. when the ess risc specifies incremental amount of the shift to be performed by writing to the applicable buffer, bits are shifted left out from the most significant end of the byte and new data from the buffer is shifted in at the least significant end. the decoder is capable of operating in block mode and step mode. regardless of the mode selected by the software, the decoder begins the decoding process with an intra-picture frame, or i-picture, which is transmitted to the decoder as a series of slices in a typical group of pictures (gop). block mode in block mode, the decoder processes one of three different types of blocks: dc luminance (y) blocks dc chrominance (uv) blocks ac blocks the decoder decodes a specified number of macroblocks of data. the resulting run length amplitude (rla) tokens are written directly to the rla output buffer. the decoder will decode up to six blocks of data and then go idle. step mode in step mode, a single token is decoded, rather than six tokens. the result can then be read by the ess risc instead of going to the applicable output buffer. after the decoder has processed the token, the decoder goes idle. video encoder the video encoder accepts digital linear ccir601 ycbcr at square pixel data rates. various color space conversion modes are provided to match the input data to the required output format. the data is then filtered to limit the bandwidth of the signals to within the supported ranges of the selected video standard. the output of the encoder is fed directly into the output fifo. the ess risc is also capable of writing variable length data into the fifo in order to insert any non- tcoeff parts into the bitstream. the risc writes variable length data to the output fifo up to 10 bits at a time. smaller tokens can be written by right justifying fewer bits in the least significant bits of the data field. since the output fifo is shared between the ess risc and the encoder, the ess risc should only write to it when the encoder is idle the encoder generates all the necessary synchronization signals for ntsc and pal standards, which are inserted into the composite and luma outputs. digital syncs are also provided for the rest of the system. the encoder also generates the corresponding sub-carrier frequency for color encoding. the encoder generates pixels at both square and nonsquare pixel data rates. this represents a pixel sampling rate of 13.5 mhz for both the ntsc and pal video data streams. these measurements assume internal 2x and 4x pixel data rate clock sources. most of the processing is performed at a 2x pixel rate. the output rate is at a 4x pixel rate, which allows the output filtering to consist of a few passive components. the encoder is a mixed digital/analog design which incorporates four 10-bit video dacs in the device architecture. this level of video dac incorporation allows the vibratto to generate composite, luma, and chroma outputs both in y/c and yuv modes. the s-video luma and chroma outputs are summed internally to generate the composite video output in y/c mode. all filtering of the luminance and chrominance signals is performed using dsp techniques. the filters are programmable so that the encoder can provide enhanced bandwidth video for s-video output, but can also provide correctly band-limited signals for composite ntsc/pal. the sync:white ratio is 40:100 ire for both ntsc and pal. on-screen display (osd) controller the 8-bit osd controller provides display support for 256 palletized colors in eight degrees of transparency and can occupy the entire viewable area of a display or a portion of the display, depending on the system design. the osd bitmap, which is stored in the reference memory, is multiplexed into the output video stream before color space conversion is performed. the vibratto performs its 3-bit blending of the on-screen display information when the ldmd bit (bit 2) of the vid_scn_osd_misc register at index 0x20001124h is set, enabling bits 2:0 of the vid_scn_osd_palette registers to establish the desired blending value for the different types of pixel modes required. the settings of mode bits 1:0 in the vid_scn_osd_misc register determine the level of blending. bits 3 of the vid_scn_osd_palette registers enable the actual blending when set at 0. modes
ess technology, inc. sam0400-103101 17 es6008/18/28/38 data sheet functional description preliminary 1 (2 bit/pixel), 2 (4 bits/pixel) and 3 (8-bit/pixel) are supported. for mode 3 (8-bit/pixel), the upper four bits of the pixel are the blend information, while the lower four bits of the pixel are the palette index and the blend information in the palette is ignored. subpicture unit (spu) decoder the subpicture unit (spu) decoder separates and decodes the run-length subpicture pixel data stream and the corresponding subpicture commands that change the color and contrast values of each pixel type for different regions. the output yuv of the spu decoder is blended with the main video screen yuv values, depending on the contrast values. the spu decoder supports four pixel types, coded 00, 01, 10, and 11. each type represents a color (yuv) and contrast value (blending value with main picture). the subpicture display area can also be divided into several horizontal stripes, each potentially with a different set of color/contrast values. each stripe can be divided vertically into a maximum of 9 vertical regions (default 0, and changes 1-8), each region containing its own color/contrast value for each pixel type. in addition, there is a highlight feature that overrides all other color/contrast information for the spu. main subpicture commands, such as spu on/off, setting the size of the subpicture display area, default color and contrast, and the pointers to the color/contrast and pixel data are done by the ess risc engine. the ess risc sets the appropriate registers in the spu, as well as the dma channel for the command and data fifos, based on these commands. spu video data framing the spu decoder receives its incoming video data in the data framing scheme depicted in figure 6. figure 6 typical subpicture data framing format during decoding, the incoming spu data packet is parsed for its pixel data and for its display control sequence information for decompression during video playback. if the last packet received by the spu decoder is less than 2048 bytes, the packet will be stuffed with extra bytes as required. coding and media content protection the vibratto supports a variety of captioning, coding and media content protection schemes that allow it to support media playback, regardless of the video encoding system used as the broadcast television standard for a specific country or geographic region. ntsc closed captioning the vibratto supports the ntsc-compatible line 21 captioning character set as required by eia-608 and by fcc part 15.119. the vibratto displays the caption information during the blanked active line time of line 21. the ascii-based line 21 character set appearing in table 6 is the same as the one found in eia-608 and in fcc part 15.119. subpicture unit header pixel data subpicture displaycontrol sequence table display ctrl sequence 0 display ctrl sequence 1 display ctrl sequence 2 display ctrl sequence x table 6 line 21 standard character set code symbol description 20 space 21 ! exclamation mark 22 ? quotation mark 23 # number sign or pound sign 24 $ dollar sign 25 % percent sign 26 & ampersand 27 ? apostrophe 28 ( open parenthesis 29 ) close parenthesis 2a lowercase a with acute accent 2b + plus sing 2c , comma 2d - hyphen or minus sign 2e . period 2f / slash 30 0 zero 31 1 one 32 2 two 33 3 three 34 4 four 35 5 five 36 6 six 37 7 seven 38 8 eight 39 9 nine
18 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary 3a : colon 3b ; semicolon 3c < less-than sign 3d = equal sign 3e > greater-than sign 3f ? question mark 40 @ at sign 41 a uppercase a 42 b uppercase b 43 c uppercase c 44 d uppercase d 45 e uppercase e 46 f uppercase f 47 g uppercase g 48 h uppercase h 49 i uppercase i 4a j uppercase j 4b k uppercase k 4c l uppercase l 4d m uppercase m 4e n uppercase n 4f o uppercase o 50 p uppercase p 51 q uppercase q 52 r uppercase r 53 s uppercase s 54 t uppercase t 55 u uppercase u 56 v uppercase v 57 w uppercase w 58 x uppercase x 59 y uppercase y 5a z uppercase z 5b [ open square bracket 5c lowercase e with acute accent 5d ] close square bracket 5e lowercase i with acute accent 5f lowercase o with acute accent 60 lowercase u with acute accent 61 a lowercase a 62 b lowercase b 63 c lowercase c table 6 line 21 standard character set (continued) code symbol description 64 d lowercase d 65 e lowercase e 66 f lowercase f 67 g lowercase g 68 h lowercase h 69 i lowercase i 6a j lowercase j 6b k lowercase k 6c l lowercase l 6d m lowercase m 6e n lowercase n 6f o lowercase o 70 p lowercase p 71 q lowercase q 72 r lowercase r 73 s lowercase s 74 t lowercase t 75 u lowercase u 76 v lowercase v 77 w lowercase w 78 x lowercase x 79 y lowercase y 7a z lowercase z 7b ? lowercase c with cedilla 7c division sign 7d ? uppercase n-tilde 7e ? lowercase n-tilde 7f solid block table 6 line 21 standard character set (continued) code symbol description
ess technology, inc. sam0400-103101 19 es6008/18/28/38 data sheet functional description preliminary the vibratto also detects the two-byte codes required by fcc part 15.119 in the bitstream so that it can recognize the embedded captioning data that would otherwise go undetected during dvd playback. each hex code shown in table 7 is preceded by 11h for data channel 1 or by 19h for data channel 2. the line 21 special character set appearing in table 7 is the same as the one found in eia- 608 and in fcc part 15.119. pal teletext captioning the vibratto supports teletext insertion and captioning typically used in the pal system. during teletext insertion, pages of text are transmitted as digital information along with the normal television signal from the video fifos of the vibratto during the blanking interval. the scan lines which are sent after the scan lines for picture sync contain the teletext data. cppm, css-2, and macrovision the vibratto implements cppm- and css2-compliant digital content protection for prerecorded audio and video media. for additional analog content protection of prerecorded media, the vibratto also supports the macrovision anti-copy process. ac-3 audio decoding (ntsc) the ac-3 audio format is used in the ntsc television format, while the mpeg-2 audio format is used in the pal television format. an ac-3 serial coded audio bitstream is comprised of a sequence of sync frames, with each frame representing 256 new audio samples, as shown in figure 7. figure 7 typical ac-3 sync audio framing as required by standard a/52 of the advanced television systems committee (atsc), the beginning of each frame starts with the sync information (si) header, followed by the bit stream information (bsi) header and audio blocks (ab) 0 through 5. the audio blocks may be followed by an auxiliary (aux) data field. at the end of each frame is an error check field that includes a crc word for error detection. an optional crc word may also be added in the si header, if desired, for greater accuracy and enhanced error detection in the decoding process. during ac-3 decoding, the compressed ac-3 data is input into the vibratto at 384 kb/s, and contains 5.1 channels of audio data. the five channels represent five full-frequency range channels of stereo audio data, while the.1 channel represents one low frequency effects (lfe) channel of audio data, usually processed as subwoofer-type audio. once the audio is decompressed into its native 5.1 channel format, the audio data can be sent directly to the speakers only if the dvd player has the required number of speakers for each channel. if the dvd player does not have the required number of speakers, the vibratto will downmix the six channels of audio data into fewer channels automatically. table 7 line 21 special character set hex example alternate description 30 see note 1 registered mark symbol 31 degree sign 32 ? 1/2 symbol 33 ? inverted (open) question mark (inverse query) 34 tm see note 1 trademark symbol 35 cents symbol 36 pounds sterling 37 musical note 38 lowercase a, grave accent 39 transparent space 3a lowercase e, grave accent 3b a lowercase a with circumflex 3c lowercase e with circumflex 3d ? lowercase i with circumflex 3e ? lowercase o with circumflex 3f ? lowercase u with circumflex 1 note: the registered and trademark symbols are used to satisfy certain legal requirements. there are various legal ways in which these symbols may be drawn or displayed. for example, the trademark symbol may be drawn with the ? t ? next to the ? m ? or over the ? m. ? it is preferred that the trade- mark symbol be superscripted, i.e., xyz tm . it is left to each individual manufacturer to interpret these symbols in any way that meets the legal needs of the user. si sync frame bsi si bsi ab 0 ab 1 ab 2 ab 3 ab 4 ab 5 aux c r c
20 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary ac-3 encoding (ntsc) during ac-3 encoding, the vibratto accepts up to 24-bit pcm words of audio. the vibratto locks the input sample rate to the output bit rate so that each ac-3 sync frame contains 1536 samples of audio (1536 samples 6 frames = 256 samples per frame). if the input audio is available in pcm format at a different sample rate than required, the vibratto performs sample rate conversion to conform to the ac-3 sampling rate before frame packing occurs. the vibratto performs high-pass filtering on the individual full-frequency input channels and removes any dc components of signals in order to allow more efficient coding to occur, while the lfe channel is low-pass filtered. the vibratto forms the coupling channel by adding all of the individual channel coefficients together and dividing the sum by 8. dividing the sum of the coefficients prevents the coupling channel from exceeding a value of 1. the vibratto determines which coefficients are to be quantized to zero and reproduced with dither on a per channel basis. when the vibratto packs the bit stream into the encoded ac-3 frame, the frame may be output in a burst or delivered as a serial data stream at a constant rate. dts multi-channel decoding the vibratto supports dts multi-channel decoding for both audio cd and dvd media playback. the vibratto supports audio post-processing, including bass management. separate downloads can be used to support stereo to 5.1 channel effects processing. the dts 6-channel decoder operates in real time and allows the channels to be monitored through the decoding cycle. the compressed data output is on a single aes-ebu channel and is clocked synchronously by the digital audio inputs. the decoding does not involve calculations that are of importance to the quality of the decoded audio. after synchronization, the decoder unpacks the compressed audio bitstream, detects and corrects any transmission- induced errors and demultiplexes the data into individual audio channels. dvd-audio (es6038 only) and mlp decoding the vibratto implements meridian lossless packing (mlp) decoding in order to support high-end audio features such as dvd-audio. during mlp decoding, up to 63 channels of 24-bit audio can be sampled at rates as high as 192 khz. the use of sampling rates this high allows the es6038 to support multichannel audio applications such as 6-channel dvd-audio. mlp decoding during mlp decoding, the vibratto manipulates each encoding process in reverse order. incoming channels are losslessly matrixed into a number of separate substreams in order for it to access a subset of the overall signal. the incoming mlp bitstreams carry all the information necessary for decoding, including instructions to the decoder, the compressed data itself, lossless testing information and crc check data. after the vibratto de- interleaves the bitstream and extracts the decoding parameters from the bitstream headers, entropy decoding is performed. the inter-channel correlations that were stripped out during the encoding process are re- established during decoding. when the bitstream is losslessly matrixed, the bitstream is successfully decoded for playback. mlp encoding during mlp encoding, the vibratto takes advantage of the fifos and various filters in the device architecture to manage the data buffering process efficiently while also ensuring the decoding process remains lossless. the vibratto detects those channels that do not use all of the available bandwidth and strips out any unnecessary inter- channel correlations using entropy coding, lossless processing and lossless matrixing. these three processes reduce the instantaneous peak data rate for best results during data sampling. hdcd decoding and filtering the vibratto performs hdcd-compliant decoding using its interpolation filtering capabilities during playback of hdcd-encoded media in audio cd, dvd and video cd modes. decoding of hdcd-encoded media occurs automatically in the vibratto when hdcd process information is detected in the audio input data. the hdcd implementation in the vibratto is primarily oriented towards the industry standard cd ? digital audio (cd-da) format, defined in the red book. the vibratto supports hdcd precision filtering for hdcd- and non- hdcd-encoded audio bitstreams alike. both 1x and 2x filtering methods are also supported. hdcd code is similar to the packet type of data sent in the ethernet network protocol in that the bitstreams include the use of descriptors. during quantization, the packet of hdcd code is inserted into the lsb of the 16-bit audio word during encoding of the cd/dvd media. the vibratto reduces the decoded average signal level of the hdcd process information in the audio input, allowing increased overhead for the expanded dynamic range.
ess technology, inc. sam0400-103101 21 es6008/18/28/38 data sheet functional description preliminary progressive scan (es6028 and es6038 only) the es6028 and es6038 both support the progressive scan reconstruction process as well as interlaced video for the ntsc and pal formats during dvd playback. the es6028 and es6038 support both baseline and progressive jpeg decoding. due to the limitation of memory, the vibratto software supports only a limited size jpeg picture. baseline pictures having more than 5120x3840 resolution, and progressive scan pictures having more than 2048x1536 resolution are not currently supported. in order to show a progressive image, the crt controllers of both the es6028 and es6038 are driven to generate and refresh the scan lines used to create the active display at a rate double that of the refresh speed used by the ntsc system. because the crt controllers of the es6028 and es6038 are driving the crt circuitry of the external video monitor to scan and refresh the active display at twice the speed, both can draw an entire frame in the same amount of time it takes to draw a single field. the progressive scan features of the es6028 and es6038 make the faster screen refresh possible, allowing for a flicker-free picture of superior quality to be displayed during dvd playback, while also reducing the number of scan lines visible to the unaided eye. the es6038 is actually faster because the processing overhead used for dvd-audio in the other vibratto devices is instead available for progressive scan operations. unlike interlaced video, every scan line of a complex video frame is refreshed when using progressive scan. since the reconstruction process of de-interlaced video is a digital process, the reconstruction process is a lossless one during a/d and d/a conversion of the bitstream. video error concealment the mpeg decoder handles bitstream errors while performing video error concealment during dvd and vcd/svcd playback. the vibratto processors all support three modes of video error concealment presented in table 8: disk error concealment when a read error occurs during dvd playback, video object units (vobus) are skipped by the vibratto. if the number of vobus to be skipped exceeds the range of the available data, the vibratto skips some sectors on the media until the presence of a new error correction control block is detected in the bitstream. device interfaces audio interface the audio interface is a bidirectional serial port that connects to an external audio adc/dac for the transfer of pcm (pulse coded modulation) audio data in i 2 s format. it supports 16-, 24-, and 32-bit audio frames. no external master clock is required. the vibratto offers two audio interface modes: 1. stereo mode using tsd0 on pin 33. 2. dolby ? digital (ac-3) and dts 5.1 channel mode using tsd[2:0] on pins [37:36, 33] the vibratto audio mode configuration is selectable, allowing it to interface directly with low-cost audio dacs and adcs. the audio port provides a standard i 2 s interface input and output and s/pdif (iec958) audio output. stereo mode is in i 2 s format while six channel dolby ? digital and dts (5.1 channel) audio output can be channeled through the i 2 s interface and s/pdif. the s/pdif interface consists of a bi-phase mark encoder, which has low skew. the transmit i 2 s interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where sampling frequency fs is usually 32 khz, 44.1 khz, 48 khz, 96 khz, or 192 khz. the audio samples for the i 2 s transmit interface can be 16, 18, 20, 24, and 32- bit samples. for linear pcm audio stream format, the vibratto supports 48 khz and 96 khz. dolby digital and dts audio only supports 48 khz. the vibratto incorporates a built-in programmable analog pll in the device architecture in order to generate a master audio clock. the mclk pin is for the audio dac clock and can either be an output from or an input to the vibratto. audio data out (tsd) and audio frame sync (tws) are clocked out of the vibratto based on the audio transmit bit clock (tbck). audio receive bit clock (rbck) is used to clock in audio data in (rsd) and audio receive frame sync (rws). dvd loader interfaces the vibratto supports the at attachment packet interface (atapi), dvd control interface (dci), integrated drive electronics (ide), and universal drive format (udf) parallel and serial port interfaces used by many types of dvd loaders. these interfaces meet the specification of many dvd loader manufacturers. table 8 video error concealment modes mode type description 0 adaptive automatically switches the vibratto between the blocky and jerky modes. 1jerky show good pictures, but not smoothly. 2blocky shows pictures smoother, but in more of a blocky fashion.
22 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary ata/ide loader interface the host interface can directly support atapi devices such as dvd drives or i/o controllers. pio modes 0 through 4 are supported. the ata/ide interface can directly control two devices through the use of the hcs1fx# and hcs3fx# signals. the ata/ide interface of the vibratto uses a command execution protocol that allows the operation of audio-cd and dvd loaders to coexist on the same type of interface cable that most computers use for cd loaders and hard disk drives. table 9 lists the packet commands and the respective command codes for atapi c/dvd devices as specified by sff-8090i. compact flash interface the vibratto provides true ide mode firmware support for the compact flash storage card interface found on a variety of removable storage cards used by digital cameras and on mp3 players. by implementing compact flash support, the vibratto can readily detect the insertion and removal of a compact flash card, which also constitutes a hot-swapping event. during a hot-swapping event, the card_detect signal is asserted by the vibratto, allowing it to determine the presence of the removable storage card fully inserted into its socket. the vibratto permits both 8- and 16-bit common memory i/o accesses with a removable storage card via the host interface. table 10 lists the cf-ata command set. table 9 packet commands for atapi c/dvd devices code command name 00h test unit ready 03h request sense 04h format unit 12h inquiry 1bh start/stop unit 1eh prevent/allow medium removal 23h read format capacities 25h read capacity 28h read (10) 2ah write (10) 2bh seek 2eh write and verify (10) 2fh verify (10) 35h synchronize cache 42h read subchannel 43h read toc/pma/atip 44h read header 45h play audio (10) 46h get configuration 47h play audio msf 4ah get event/status notification 4bh pause/resume 4eh stop play/scan 51h read disc information 52h read track/rzone information 53h reserve track/rzone 54h send opc information 55h mode select (10) 58h repair rzone 5ah mode sense (10) 5bh close track/rzone/session/border 5dh send cue sheet a1h blank a2h send event a3h send key a4h report key a6h load/unload medium a7h set read ahead a8h read (12) aah write (12) ach get performance adh read dvd structure b6h set streaming b9h read cd msf bah scan bbh set cd speed bch play cd bdh mechanism status beh read cd bfh send dvd structure table 10 cf-ata command set class command code 1 check power mode e5h or 98h 1 execute drive diagnostic 90h 1 erase sector(s) c0h 1 identify drive ech 1 idle e3h or 97h 1 idle immediate e1h or 95h 1 initialize drive parameters 91h 1 read buffer e4h 1 read long sector 22h or 23h 1 read multiple e4h 1 read sector(s) 20h or 21h 1 read verify sector(s) 40h or 41h 1recalibrate 1xh 1 request sense 03h 1 security disable password f6h 1 security erase prepare f3h 1 security erase unit f4h 1 security freeze lock f5h 1 security set password f1h 1 security unlock f2h table 9 packet commands for atapi c/dvd devices
ess technology, inc. sam0400-103101 23 es6008/18/28/38 data sheet functional description preliminary dvd control (dci) loader interface the dci interface routes incoming dvd bitstreams from the dci loader to the vibratto via the dvd descrambler so that the dvd bitstreams can be decoded for decompression and playback. dci_fds# indicates the beginning of each sector on the dvd medium. the dci_err# signal indicates the error per data byte. dci_ack# indicates an acknowledge signal from the servo that a data byte is ready to be transferred. the dci_req# line is used by the vibratto to inform the servo that it is ready to receive data. universal disk format (udf) loader interface the udf 2.01 loader interface routes incoming dvd bitstreams from a udf loader, typically a cd-r or dvd-r loader, to the vibratto via the dvd descrambler so that the dvd bitstreams can be decoded for decompression and playback. the udf entity identifier definitions are listed in table 11. table 11 udf entity identifier definitions host interface the host interface of the vibratto allows communication between the risc and an external host, and is comprised of three ports. two of these ports are the 8-bit wide debug and command ports, with the third being the 16-bit wide dma port. the command port transfers control and status information between the host and the vibratto. the external host controls the vibratto through the command port. the debug port provides a path to the risc core for debugging purposes. this allows programmers access to the state of the hardware and the software without disturbing the command or dma ports. the dma port transfers data to be multiplexed with the audio and video data in an encoded bitstream. this mechanism allows applications such as file transfers to occur. additionally, the dma port can carry both the audio and the encoded bitstream. the host interface has two registers that control the operation of the flags and interrupts, r_hostrqstat and r_hostmask for the risc side and h_hostrqstat and h_hostmask for the host side. flags indicate the readiness of the vibratto to accept or supply data over the host interface dma channel. interrupts may be used for exception indication from risc-to-host or from host-to-risc. the interrupts are maskable. the pulse width high times of the hrdreq# and hwrreq# signals are defined as minimum values only. the maximum values of these parameters are software dependent. the internal dma channel bandwidth depends upon the presence of other dma operations in the vibratto. system sram interface the system sram interface controls access to optional external sram which can be used for risc code, stack, and data. the sram bus supports four independent address spaces, each having programmable bus width and wait states. the interface can support not only sram but also rom/eprom and memory-mapped i/o ports for standalone applications. the vibratto inserts from 1 to 32 wait states into each cycle, with each wait state being one clock cycle long. risc accesses can involve just one wait state. when switching from a low speed bank to a high speed bank, the turnoff delay of the low speed bank can overlap the first access of the high speed bank. to prevent data corruption, bank select delay time t bs_dt is programmable for each sram bank from 0 to 3t states. 1 seek 7xh 1 set features efh 1 set multiple mode c6h 1 set sleep mode e6h or 99h 1 stand by e2h or 96h 1 stand by immediate e0h or 94h 1 translate sector 87h 1 wear level f5h 2format track 50h 2 write buffer e8h 2 write sector(s) 30h or 31h 2 write long sector 32h or 33h 2 write sector(s) w/o erase 38h 3 write verify 3ch 3 write multiple c5h 3 write multiple w/o erase cdh entity identifier description osta udf compliant contents of the specified volume comply with domain specified by the udf specification. udf lv info contains additional logical volume information. udf freeappeaspace contains free unused space within the application extended attributes space. udf dvdcgms info contains dvd copyright manage- ment information. udf virtual partition describes udf virtual partition. udf sparable partition describes udf sparable partition. udf sparing table contains information for handling defective areas on the media. table 10 cf-ata command set (continued) class command code
24 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary the signals for the sram bus are generated from the internal risc clock and are timed in integer multiples of clock cycles, except for the write strobe, which is delayed by one-half cycle from the address setup and advanced one-half cycle from the start of the next access cycle. the sram interface signal skew may vary with the vibratto speed grade. tdm interface the vibratto implements a high-speed, bidirectional serial bus known as a tdm interface that supports a number of high-speed serial protocols. the tdm interface can also act as a general-purpose 16-mbps serial link when not constrained by tdm protocols. the tdm interface provides an easy connection between the vibratto and available communications chips. the tdm interface is a time-division-multiplexed bus that multiplexes byte data on up to 64 channels. time slot 0 starts after n (which can be set in the xmt/rcvdelay register) clocks after the frame starts. each slot is eight clock periods long, and either transmits or receives byte data during a write cycle or a read cycle. immediately after slot 0 completes, slot 1 starts and so on. each channel is allocated a different time slot on the bus, and the vibratto can be set to send and receive data in any combination of different time slots. data is assumed to be ordered by time slot; e.g., if time slots 6, 8, and 17 are used, the first dma byte sent to memory would be in time slot 6, followed by time slots 8 and 17 in order. reordering must be done in software. the interface consists of frame sync signal tdmfs, data transmit and receive signals tdmdx and tdmdr, external buffer enable signal tdmtsc# and bit clock signal tdmclk. the timing of the data transfer is externally controlled. the tdm interface can support a number of different timings. the tdm interface supports both forms 1 and 2 of the xa mode format as required by iso 9660. the tdm interface can transfer data at a maximum rate of 16 mbps, with a more typical configuration supporting a data rate of up to 4.096 mbps with a frame sync frequency of 8 khz. the tdm interface hardware is flexible enough to interface with a wide range of communications chips for isdn, pabx, lan and wan connectivity. the vibratto interfaces especially well with those devices that support the concentration highway interface (chi) bus, isdn-oriented modular revision 2 (iom-2) interface, and multi-vendor integration protocol (mvip). the tdm interface programmability includes independent receive, transmit, and frame sync clock edge selection and independent receive and transmit data offsets. tdm operation and bit settings 1. to turn on the tdm, set the tdm_rst bit (bit 5) in the tdmctl0 register to 0, then to 1. 2. to reset the tdm internal registers, set tdm_tstbit (bit 10) in the tdmctl0 register to 1, then to 0. 3. the slot registers must be set, there are no default values. 4. when using 2x clock, the crefphase bit has to be set and the p bit in the xmt/rcvdelay register must be 0. 5. when using 2x clock, the values in tables must be multiplied by 2. 6. fe, xce, xmt_delay table: 7. fe, xce, rcv_delay table: xmt_delay fe xce 01234567 note 0 0 357911131517 start x-mit on rising 0 1 4 6 8 10 12 14 16 18 start x-mit on falling 1 0 357911131517 start x-mit on falling 1 1 4 6 8 10 12 14 16 18 start x-mit on rising 1 2 3 4 5 6 7 8 9 10111213141516 framesync clk xce=0, xmit_delay=0 xce=1, xmit_delay=0 xce=0, xmit_delay=1 xce=1, xmit_delay=1 1 2 3 4 5 6 7 8 9 10111213141516 framesync fe=1 clk xce=0, xmit_delay=0 xce=1, xmit_delay=0 xce=0, xmit_delay=1 xce=1, xmit_delay=1 fe=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 framesync fe=0 clk rce=0, rcv_delay=0 rce=1, rcv_delay=0 rce=0, rcv_delay=1 rce=1, rcv_delay=1 framesync fe=1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk rce=0, rcv_delay=0 rce=1, rcv_delay=0 rce=0, rcv_delay=1 rce=1, rcv_delay=1
ess technology, inc. sam0400-103101 25 es6008/18/28/38 data sheet functional description preliminary vacuum fluorescent display (vfd) interface the vibratto provides hardware support for the vacuum fluorescent display (vfd) interface in dvd player designs. the vfd_ctrl register at index 0x200013cch is programmed by the software for supporting the control and format functions in the first access, and enables the interface in the second access. the vfd_data register at index 0x200013d0h, along with the aux_mode register at index 0x20001340h both act as containers for an external vfd device to read data from it and write vfd clock and data to it during normal operations. the sys_status register at index 0x200013d8h and the ir_diff register at index 0x200013dch provide additional hardware support for remote control operations. video memory interface the vibratto provides a glueless 16-bit interface to dram memory devices used as video memory for a dvd player. the maximum amount of memory supported is 16 mb of synchronous dram (sdram). the memory interface is configurable in depth to support 128-mb addressing. the memory bus interface generates all the control signals to interface with external memory. the vibratto supports different configurations using the memory configuration bits sdcfg[1:0] (bits 12:11), the sd8bit bit (bit 14), and sd64m bit (bit 15) in the buscon_dram_control register located at index 0x20008100h. configurations can be implemented in many ways. table 12 lists the typical sdram configurations used by the vibratto. the memory interface controls access to both external sdram or edo memories, which can be the sole unified external read/write memory acting as program and data memory as well as various decoding and display buffers. at high clock speeds, the vibratto memory bus interface has sufficient bandwidth to support the decoding and displaying of ccir601 resolution images at full frame rate. sdram considerations the vibratto uses sdram with a programmed cas# latency of three clocks (cl=3) and sequential burst of full page length. performance based on sdram is double that of edo. sdram must be software configured before any memory access. the programmable sdram refresh period can be modified to meet any desired configuration. sdram address mapping the memory address (la) is mapped to the dma address, which is formed by addr in the buscon_dma_addr registers. the result is then converted into the dram control signals using the sdcfg[1:0] configuration bits (bits 12:11) and the sd8bit bit (bit 14) in the buscon_dma_control register located at index 0x20008100h. sdram configuration requirements table 13 shows sdram memory size configurations, each with its corresponding signal pins. rcv_delay ferce01234567 note 0 0 4 6 8 10 12 14 16 18 sampled on falling ? 1357911131517 sampled on rising ? 0 4 6 8 10 12 14 16 18 sampled on rising ? 1357911131517 sampled on falling table 12 typical sdram configurations size (mb) bit order memory configuration sd64m sd8bit sdcfg1 sdcfg0 2.0 0 0 0 1 1 pc: 512kx16x2 (16 mb) 4.0 0 0 0 0 2 pcs: 512kx16x2 (16 mb) 4.0 0 1 0 1 2 pcs: 1mx8x2 (16 mb) 8.0 0 1 0 0 4 pcs: 1mx8x2 (16 mb) 8.0 1 0 x x 1 pc: 1mx16x4 (64 mb) 16.0 1 0 x x 2 pc: 1mx16x4 (64 mb) 16.0 1 1 x x 2 pc: 2mx8x4 (64 mb) 16.0 1 1 x x 1 pc: 2mx16x4 (128 mb) table 13 sdram configurations and signal pins size (mb) sdram 0 sdram 1 sdram2 sdram3 memory type 2.0 dcas# dras0# dcs0# db[0:15] 512kx16x2 (16 mb) 4.0 dcas# dras0# dcs0# db[0:15] dcas# dras0# dcs1# db[0:15] 512kx16x2 (16 mb) 4.0 dcas# dras0# dcs0# db[0:7] dcas# dras0# dcs1# db[8:15] 1mx8x2 (16 mb) 8.0 dcas# dras0# dcs0# db[0:7] dcas# dras0# dcs0# db[8:15] dcas# dras0# dcs1# db[0:7] dcas# dras0# dcs1# db[8:15] 1mx8x2 (16 mb) 8.0 dcas# dras0# dcs0# db[0:15] 1mx16x4 (64 mb) 16.0 dcas# dras0# dcs0# db[0:15] dcas# dras0# dcs1# db[0:15] 1mx16x4 (64 mb)
26 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet functional description preliminary video interface video display output the video output section controls the transfer of video frames stored in memory to the internal tv encoder of the vibratto. the output section consists of a programmable crt controller capable of operating either in master or slave mode. figure 8 shows the display timing on the screen. the video output section features display fifos to buffer outgoing luminance and chrominance data while also performing yuv4:2:0 to yuv4:2:2 conversion. arbitrary horizontal decimation and interpolation is achieved by a polyphase filter. together with programmable line dropping/duplication circuitry and micro-code based post- processing running on the video processor, the vibratto is capable of arbitrating image conversion. examples include sif to ccir601, letter-box, ntsc to pal, and pal to ntsc conversions. video bus the vibratto video bus transfers digital video pixels out of the chip. in standalone applications the video bus will be connected to a monitor or an lcd panel. in workstation applications, the output bus will feed an overlay circuit so that the output video appears in a window of the graphical user interface (gui). the video bus has 8 yuv data pins that transfer luminance and chrominance (yuv) pixels in ccir601 pixel format (4:2:2). in this format, there are half as many chrominance (u or v) pixels per line as luminance (y) pixels; there are as many chrominance lines as luminance. figure 8 video output timing safe caption area the vibratto draws the safe caption area required by fcc part 15.119 as shown in figure 7. figure 9 safe caption area the dimensions of the safe caption area are listed in table 14. table 14 safe caption area dimensions 16.0 dcas# dras0# dcs0# db[0:7] dcas# dras0# dcs0# db[8:15] 2mx8x4 (64 mb) 16.0 dcas# dras0# dcs0# db[0:15] 2mx16x4 (128 mb) table 13 sdram configurations and signal pins size (mb) sdram 0 sdram 1 sdram2 sdram3 memory type label dimension percent of picture height a television picture height 100.0 b television picture width 133.33 c height of safe caption area 80.0 d width of safe caption area 106.67 e vertical portion of safe caption area 10.0 f horizontal portion of safe caption area 13.33 0,0 vblank hsync vsync hsyncwidth start vstart vend vsync period vblank stop vsync width hsyncperiod main window hblankstop hstart hend hblankstart location 0,0 is the upper left corner of the screen. osd active display area spu a b c d e f
ess technology, inc. sam0400-103101 27 es6008/18/28/38 data sheet functional description preliminary video post-processing the vibratto video post-processing circuitry provides support for the color conversion, scaling, and filtering functions through a combination of special hardware and software. horizontal up-sampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate non-integer interpolations. vertical scaling is achieved by repeating and dropping lines in accordance with the applicable scaling ratio. figure 10 shows the video post- processing functional blocks. the first two processing steps are performed by the video processor core. video post-processing can be applied on the decoded images to improve the picture quality. figure 10 video post-processing the next stage in the processing, applicable only to low resolution mpeg-1 video, is an interlacing filter that generates even and odd fields from decoded frames for applications that use a tv screen. the filter improves both the spatial and temporal appearance of the decoded images on interlaced displays. following the interlacing filter is an interpolation section that uses bilinear interpolation to increase the resolution of the chrominance components by a factor of two in the vertical dimension. this interpolation section converts from the mpeg chrominance subsampling to that used by ccir601. the resulting yuv pixels can then be passed through a 7-tap horizontal interpolation filter that increases the horizontal resolution of the image by up to four times. the horizontal filter automatically chooses between five sets of filter coefficients based on the fractional component of the new position of the pixel in the video data stream. the filter coefficients are 8 bits wide. the filter length is selectable as 1, 3, 5, or 7 taps. the relationship between pclk2xscn and internal risc clock is shown in table 15. table 15 ess risc clock relationship to pixel clocks video timing the video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. the double clock typically is used for tv displays, the single for computer displays. pclkqscn is ignored in 1x clock mode. the timing of the syncs and odd/even field indication is shown in figure 12 and figure 13. the output video field indication is done by modifying the relative positions of vsync and hsync. at the start of an even field, the horizontal and vertical sync pulses will start on the same clock edge; in odd fields the horizontal sync pulse will be delayed by one clock cycle. the polarity of both horizontal and vertical syncs is programmable. figure 11 8-bit yuv input timing figure 12 horizontal video timing figure 13 vertical video timing output osd horizontal uv vertical interlacing vertical post- processing dram osd data from dram vertical scale up horizontal scale up yuv 4:2:2 generate interpolate filter interpolate interpolate hardware improve by up to 4 times vertical only interlaced fields frame buffer by any amount image quality subpicture data spu video processor core from dram decode taps restrictions frequency 3 pixel rate < (internal risc clk)/2 27 mhz 5 pixel rate < (internal risc clk)/3 20 mhz 7 pixel rate < (internal risc clk)/4 default 13.5 mhz pclkqscn hsync yuv[7:0] u0 y0 v0 y1 u2 pclkqscn hsync# min 128 pixels, max 4095 pixels min 4 pixels hsync# vsync# min 8 lines, max 4095 lines min 2 lines
28 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary registers host interface (host side) registers this section describes the host interface (host side) registers of the vibratto. h_hostdmaport (0x0, r/w) the host interface dma port register contains memory and i/o data transferred to and from the risc. after reset, it is initialized to 0x0000. h_hostvcxport (0x1, r/w) the host interface command port register contains control and status data transferred to and from the risc. after reset, it is initialized to 0x00. h_hostdbgport (0x2, r/w) the host interface debug port register transfers data to and from the risc during debugging. after reset, it is initialized to 0x00. h_hostctl (0x3, r/w) the host interface control register enables and disables the host-to-risc and risc-to-host interrupt capabilities of the up68d01-2811. after reset, it is initialized to 0x00. h_hostmask (0x4, r/w) the host interface irq mask register after reset, it is initialized to 0x00. host interface (dma port) data 15:0 host interface (command port) data 7:0 host interface (debug port) data 7:0 h2r_irq isel osel clr_rirq 76:4 3:10 bits name description 7 h2r_irq host to risc irq enable. writing a 1 to this bit sets the host to risc irq flag. 6:4 osel [2:0] select which tre and dw bits are sent to the hrdreq read request pins. hrdreq = (dma_dw and osel_0) or (vcx_dw and osel_1) or (dbg_dw and osel_2). 3:1 isel[2:0] select which tre and dw bits are sent to the hwrreq (write request) pins. hwrreq = (dma_tre and isel_0) or (vcx_tre and isel_1) or (dbg_tre and isel_2). 0clr_ rirq risc-to-host irq clear. writing a 1 to this bit clears the risc to host irq. endn_ sel dbg_ tre dbg_dw dma_ tre dma_dw vcxi _tre vcxi _dw r2r_irq 76543210 bits name description 7 endn_ sel host side endian select. when set, this bit switches the upper and lower bytes of data sent as writes to the host interface dma port register. 1 = switch upper/lower bytes. 6dbg_ tre debug transmit register empty enable. 5dbg dw debug data waiting 1 = host ready to read debug data from ess risc. 4dma tre dma transmit register empty. 1 = host ready to send dma data to ess risc. 3dma dw dma data waiting 1 = host waiting to read data from ess risc. 2vcxi tre vcxi transmit register empty 1 =host ready to send data to ess risc. 1vcxi dw vcxi data waiting 1 = host waiting to read data from ess risc. 0r2r irq interrupt flag 1 = set by ess risc as ready to receive signal to the host.
ess technology, inc. sam0400-103101 29 es6008/18/28/38 data sheet registers preliminary h_hostirqstat (0x5, r) this register reads the status of interrupts from the risc to the host; 1=irq, 0=no irq. video interface registers the following describes the video interface registers. video output registers vid_scn_hstart (0x20001000h, w) the video screen horizontal start register contains the 13-bit horizontal pixel starting address of the active window for the screen. vid_scn_hend (0x20001004h, w) the video screen horizontal end register contains the 13- bit horizontal pixel end address of the active window for the screen. vid_scn_vstart (0x20001008h, w) the video screen vertical start register contains the 13-bit vertical scan line starting address of the active window for the screen. vid_scn_vend (0x2000100ch, w) the video screen vertical end register contains the 13-bit vertical scan line ending address of the active window for the screen. h2rirq dbgtre dbgdw dmatre dmadw vcxitre vcxidw r2hirq 76543210 bits name description 7h2r irq interrupt flag set by the host as a signal to the risc. 6dbg tre debug transmit register empty (ok for host to send data to the risc). 5dbg dw debug data waiting (host needs to read data from the risc). 4dma tre dma transmit register empty (ok for host to send data to the risc). 3dma dw dma data waiting (host needs to read data from the risc). 2vcxi tre vcxi transmit register empty (ok for host to send data to the risc). 1vcxi dw vcxi data waiting (host needs to read data from the risc). 0r2h irq interrupt flag set by the risc as a signal to the host. ? hstart 15:13 12:0 bits name description 15:13 ? reserved. 12:0 hstart horizontal start of active window. ? hend 15:13 12:0 bits name description 15:13 ? reserved. 12:0 hend horizontal end of active window. ? vstart 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vstart vertical start of active window. ? vend 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vend vertical end of active window.
30 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary vid_scn_vertirq (0x20001010h, w) the video screen vertical line interrupt write-only register is selectable by software and contains the line in which a vertical interrupt will occur. line 0 is the top of the screen (leading edge of vsync pin). typical is to set an interrupt either just before or just after the active region of the screen. vid_scn_hblank_start (0x20001014h, w) the video screen horizontal blanking start write-only register contains the 13-bit starting address of the horizontal blanking interval. vid_scn_hblank_stop (0x20001018h, w) this register contains the ending address of the horizontal blanking. vid_scn_vblank_start (0x2000101ch, w) the video screen vertical blanking start register contains the starting address of the vertical blanking interval. vid_scn_vblank_stop (0x20001020h, w) this register contains the ending address of the vertical blanking. vid_scn_hsyncwidth (0x20001024h, w) this register contains the width of the horizontal sync pulse. it is needed only if sync direction is output. ? vertirq 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vert irq line where a vertical interrupt will occur. ? hblank_start 15:13 12:0 bits name description 15:13 ? reserved. 12:0 hblank_ start start of horizontal blanking interval. ? hblank_stop 15:13 12:0 bits name description 15:13 ? reserved. 12:0 hblank stop end of horizontal blanking. ? vblank_start 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vblank start start of vertical blanking interval. ? vblankstop 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vblank stop end of vertical blanking. ? hsyncwidth 15:13 12:0 bits name description 15:13 ? reserved. 12:0 hsync width horizontal sync pulse width. bits name description
ess technology, inc. sam0400-103101 31 es6008/18/28/38 data sheet registers preliminary vid_scn_hsyncperiod (0x20001028h, w) this register contains the period of the horizontal sync pulse. it is needed only if sync direction is output. vid_scn_vsyncperiod (0x2000102ch, w) this register contains the period of the vertical sync pulse. it is needed only if sync direction is output. vid_scn_vsyncpixel (0x20001030h, w) this register defines which pixel vsync will change on. the number of pixels delayed from hsync that vsync will change on (rise or fall). this is needed only if sync direction is output. vid_scn_vsyncwidth (0x20001034h, w) this register defines the width of the vertical sync pulse. it is needed only if sync direction is output. vid_scn_vertcount (0x20001036h, r) for testing only. this register contains the current line of the vertical counter. starts at vsync line 0. vid_scn_horizcount (0x20001038h, r) for testing only. this register contains the current pixel of the horizontal counter. starts at hsync pixel 0. vid_scn_counter_ctl (0x2000103ch, w) this register contains miscellaneous counter control bits. after reset, it is initialized to 0x00. ? hsyncperiod 15:13 12:0 bits name description 15:13 ? reserved. 12:0 hsync period horizontal sync period. ? vsyncperiod 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vsync period vertical sync pulse period. ? vsyncpixel 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vsync pixel pixel on which vsync will change. ? vsyncwidth 15:6 5:0 bits name description 15:6 ? reserved. 5:0 vsync width vertical sync pulse width. ? vertcount 15:13 12:0 bits name description 15:13 ? reserved. 12:0 vert count current pixel of the vertical counter. ? horizcount 15:13 12:0 bits name description 15:13 ? reserved. 12:0 horiz count current pixel of the horizontal counter. ? invblnk 0 invhs invvs mstr mode 7:5 4 3 2 1 0 bits name description 7:5 ? reserved. 4inv blnk inverted blank sync. 1 = blank is active low. 0 = otherwise. 3 ? set at zero. 2 invhs inverted horizontal sync. 1 = horizontal sync is active low. 1 invvs inverted vertical sync. 1 = vertical sync is active low. 0 = otherwise. 0mstr mode master mode select. 1= vibratto drives sync pins. 0= syncs input to vibratto.
32 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary vid_scn_outputcntl (0x20001040h, r/w) this register contains the mode bits used to control video output. vid_scn_iterfacecntl (0x20001048h, r/w) this register contains the mode bits used to control video output. vid_scn_resets (0x20001050h, r/w) resets for the video screen section. these bits are set to 1 on reset. ? zerob bypass 3tap _en coef ldmd clamp _en inv msb yuv 8bit ts mode 15:9 8 7 6 5 4 3:2 1 0 bits name description 15:9 ? reserved. 8 zerob zero boundary. 1 = use zeroes for pixels outside of the bor- der for horizontal filtering. 0 = use the pixel on the edge. 7 bypass horizontal filter bypass. 1 = bypass horizontal filter. 0 = use horizontal filter. 6 3tap_en 3/7 tap filter select. 1 = 3-tap horizontal filter selected. 0 = 7-tap horizontal filter selected. 5coef ldmd 0 = uv is selected first. 1 = y is selected first. 4clamp _en clamp enable. 1 = clamp output according to ccir601 min/max values. 0 = no clamping. 3:2 invmsb [1:0] invert msb yuv output [1:0]. invmsb[1] = invert msb of y output. invmsb[0] = invert msb of uv output. 1 yuv8bit 8-bit yuv output enable. 1 = 8-bit yuv output enabled 0 = invalid. 0 tsmode toggle select mode. 1 = y is first in 8-bit mode. 0 = uv is first in 8-bit mode. ? mm mbm invhs invvs invb 1pe epu mck clkdiv ipq ck1m 15:12 11 10 9 8 7 6 5 4 3:2 1 0 bits name description 15:12 ? reserved. 11 mm master mode. 1 = vibratto drives sync signals. 0 = slave mode. 10 mbm master blanking mode 1 = vibratto determines blanking region. 0 = slave mode. 9 invhs invert horizontal sync. 1 = horizontal sync inverted. 8 invvs invert vertical sync. 1 = vertical sync inverted. 7 invb invert blanking. 1 = blanking interval inverted. 6 1pe first pixel even. 1 = first pixel of active region is even. 5 epu even pixel u select. 1 = even pixel is u pixel. 0 = even pixel is v pixel. 4 mck master pixel clock mode. 1 = vibratto drives master clock. 3:2 clk_div [1:0] clock divider [1:0]. vibratto drives pixel clocks: i 1 ipq invert pclkqscn. 1 = pclkqscn pin inverted. 0ck1m clock1x mode. 1 = use pclk2xscn or internal 27 mhz pclk 0 = use 13.5 mhz pclkqscn. ? r_pan 1 r_y r_uv r_hf r_cnt dmago 15:8 7 6:5 4 3 2 1 0 bits name description 15:8 ? reserved. 7 r_pan reset pan and scan. 1 = reset pan and scan function (default). 6:5 1 reserved. always 1. 4r_y reset y fifo. 1 = reset y fifo (default). 3 r_uv reset uv fifo. 1 = reset uv fifo (default). 2 r_hf reset horizontal filter. 1 = horizontal filter reset (default). 1 r_cnt reset counter. 1 = counter reset (default) 0 dmago dma enable. 1 = dma enabled (default). bits name description clk div1 clk div0 description 00 screen clock depends on clk1xmod (default). 01 13.5 mhz screen clock is half of input pixel clock. 1x 6.75 mhz screen clock is one-quarter of input pixel clock.
ess technology, inc. sam0400-103101 33 es6008/18/28/38 data sheet registers preliminary vid_scn_status (0x20001058h, r) this register contains the status bits for the video section. on screen display (osd) controller registers vid_scn_osd_hstart (0x20001110h, r/w) this register contains the horizontal starting address (referenced from active window). vid_scn_osd_hend (0x20001114h, r/w) this register contains the horizontal ending address (referenced from active window). vid_scn_osd_vstart (0x20001118h, r/w) this register contains the vertical starting address (referenced from active window). vid_scn_osd_vend (0x2000111ch, r/w) this register contains the osd vertical ending address (referenced from active window). vid_scn_osd_misc (0x20001124h, r/w) this register contains miscellaneous control and status bits in the osd controller. o_e blnk hs vs vact act act d1 act d2 act d3 1p nl nf np ep up up d! 15 14131211 10 9 8 7 6543210 bits name description 15 o_e vs/hs odd or even field status. 1 = odd field. 0 = even field. 14 blnk status of internal blanking. 13 hs status of internal horizontal sync. 12 vs status of internal vertical sync. 11 vact vertical active. 10 act active screen for fifo. 9 act_d1 active horizontal filter signal. 1 = horizontal filtering signal active. 8 act_d2 active osd/spu/mixer signal. 1 = osd/spu/mixer signal active. 7 act_d3 active output port signal. 1 = output port signal active. 6 1p first active pixel for fifo. 1 = first active pixel selected. 5 nl new line. 1 = first pixel of new line selected. 4 nf new field. 1 = first pixel of new field selected. 3np new pixel. 1 = one clock cycle of every pixel clock cycle selected. 2 ep even pixel for fifo. 1 = current pixel selected for fifo is even. 1 up u pixel horizontal filter select. 1 = current pixel uses u for horizontal filtering. 0 = current pixel uses v for horizontal filtering. 0 upd1 u pixel mixer select. 1 = current pixel uses u for osd/spu/mixer. 0 = current pixel uses v for osd/spu/mixer. ? osd_hstart 15:13 12:0 bits name description 15:13 ? reserved. 12:0 osd_ hstart horizontal starting address. ? osd_hend 15:13 12:0 bits name description 15:13 ? reserved. 12:0 osd_ hend horizontal ending address. ? osd_vstart 15:13 12:0 bits name description 15:13 ? reserved. 12:0 osd vstart vertical starting address . ? osd_vend 15:13 12:0 bits name description 15:13 ? reserved. 12:0 osd_ vend vertical ending address. lat_int reset_overlay pal_index [1:0] inten ldmd mode 76 5:4321:0 bits name description 7 lat_int latched interrupt. this is a read-only bit. 6 reset_ overlay reset overlay section (set to 1 at reset). 5:4 pal_ index upper 2 bits of palette address when in 2- bit mode. 3 inten interrupt enable. 2 ldmd enable palette load.
34 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary vid_scn_ osd_palette (0x20001140h?0x2000117ch, r/w) these 16 registers contain the osd palette. for mode 3 (8-bit/pixel) the upper 4 bits of the pixel are the blend information, the lower 4 bits are the palette index and the blend information in the palette is ignored. subpicture unit (spu) decoder registers this section describes the subpicture unit (spu) decoder registers. sp_spctl (0x20001600h, r/w) this register is the sub-picture control register. after reset, it is initialized to 0x000h. write a ? 1 ? to the corresponding bit to mask the interrupt. sp_vcnt (0x20001700h, r/w) this register is the vertical counter value register. after reset, it is initialized to 0x07fh. 1:0 mode 0 0 = bypass (initializes to 00 at reset). 0 1 = 2 bit/pixel. 1 0 = 4 bit/pixel. 1 1 = 8 bit/pixel. yv 15:12 11:8 ublnd_on/offblnd 7:4 3 2:0 bits name description 15:12 y upper 4 bits of luminance data (lower 4 bits are 0). 11:8 v upper 4 bits of v chrominance data (lower 4 bits are 0). 7:4 u[ upper 4 bits of u chrominance data (lower 4 bits are 0). 3 blnd_ on/off blending/transparency enable. 1 = blending off; transparency on. 0 = blending on; transparency off. 2:0 blnd blending value: value blnd value blnd 0 1/8 4 5/8 1 2/8 5 6/8 2 3/8 6 7/8 3 4/8 7 8/8 finalpixel = blnd x palette value + (1 - blnd) x original pixel. ? reset2 sp_rel 15:10 9 8 ccirq en risc_ done spuon reset rleat dcseat rlirqen dcsirq en 76543210 bits name description bits name description 15:10 ? reserved. 9 reset2 write only: 1 = reset part of spu (i.e., similar to reset at the end of a frame); the fifos and the state machines are reset, but not the registers (one clock cycle). 0 = nothing. need to kill dma and set this bit before every frame if dma is not exact. 8 sp_rel 0 = coordinates for changes within the sub- picture are relative to the main video display area. 1 = coordinates for changes within the sub- picture are relative to the sub-picture. 7 ccirq_ en 1 = col/con command error interrupt enable. 0 = disabled. 6 risc_ done write only: 1 = risc done with decoding sp (one clock cycle). 0 = otherwise. 5 spuon sub-picture on/off: 1 = sub-picture is on. 0 = sub-picture is off. 4 reset write only: 1 = reset spu decoder (one clock cycle). 0 = otherwise. 3 rleat risc eat rlfifo: 0 = risc read fifo output only, no change in value. 1 = risc read fifo, causes it to eat byte. 2 dcseat risc eat dcsfifo: 0 = risc read fifo output only, no change in value. 1 = risc read fifo, causes it to eat byte. 1 rlirq en 1 = rlfifo irq enable. 0 = rlfifo irq disable. 0 dcsirq en 1 = dcsfifo irq enable. 0 = dcsfifo irq disable. ? sp_vcnt 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_vcnt spu vertical count value.
ess technology, inc. sam0400-103101 35 es6008/18/28/38 data sheet registers preliminary sp_vcntreg (0x20001704h, r/w) this register is the vertical counter initial value register. after reset, it is initialized to 0x7feh sp_hcnt (0x20001708h, r/w) this register is the horizontal counter value register. after reset, it is initialized to 0x0h. sp_hcntreg (0x2000170ch, r/w) this register is the horizontal counter initial value register. after reset, it is initialized to 0x000h. sp_vstart (0x20001710h, r/w) sp_vstart is the start line of subpicture display area register. after reset, it is initialized to 0x3ffh. sp_vend (0x20001714h, r/w) sp_vend is the end line of subpicture display area register. after reset, it is initialized to 0x3ffh. sp_hstart (0x20001718h, r/w) sp_hstart is the horizontal start pixel of the subpicture display area register. after reset, the contents of this register is initialized to 0x3ffh. sp_hend (0x2000171ch, r/w) sp_hend is the horizontal pixel end of the subpicture display area register. after reset, it is initialized to 0x3ffh. sp_subvcnt (0x20001720h, r/w) sp_subvcnt is the subpicture vertical count register within the subpicture display area register. after reset, it is initialized to 0x3ffh. ? sp_vcnt_init 15:10 9:0 bits name description 15:11 ? reserved. 10:0 sp_vcnt init spu vertical count initial value. ? sp_hcnt 15:11 10:0 bits name description 15:11 ? reserved. 10:0 sp_hcnt spu horizontal count value. ? sp_hcnt_init 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_hcnt init spu horizontal count initial value. ? sp_vstart 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_vstart spu vertical start line value. ? sp_vend 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_vend spu vertical start line value. ? sp_hstart] 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_hstart spu horizontal start pixel value. ? sp_hend 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_ hend spu horizontal end pixel value. ? sp_subvcnt 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_sub vcnt spu subpicture display vertical count value.
36 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary sp_subhcnt (0x20001724h, r/w) sp_subhcnt is the horizontal pixel count within the subpicture display area register. after reset, it is initialized to 0x3ffh. sp_vcstart (0x20001728h, r/w) sp_vcstart is the start line of current sub-picture change register. after reset, it is initialized to 0x3ffh. sp_vcend (0x2000172ch, r/w) sp_vcend is the end line of current subpicture change register. after reset, it is initialized to 0x3ffh. sp_hivs (0x20001730h, r/w) sp_hivs is the current subpicture highlight vertical start line display area register. after reset, it is initialized to 0x3ffh. sp_hive (0x20001734h, r/w) sp_hive is the current subpicture highlight vertical end line display area register. after reset, it is initialized to 0x3ffh. sp_hihs (0x20001738h, r/w) sp_hihs is the current subpicture highlight horizontal start pixel display area register. after reset, it is initialized to 0x3ffh. sp_hihe (0x2000173ch, r/w) sp_hihe is the current subpicture highlight horizontal end pixel display area register. after reset, it is initialized to 0x3ffh. sp_hstart1-8 (0x20001740h ? 0x200175ch, r/w) sp_hstart [1:8] are the pixel number for start of changes 1 through 8 register. after reset, the contents of these registers are initialized to 0x3ff.the register bit tables for all these registers are identical to the one shown above. ? sp_subhcnt 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_sub hcnt spu subpicture display horizontal pixel count value. ? sp_vcstart 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_vc start spu current subpicture display vertical start scan line value. ? sp_vcend 15:10 9:0 bits name description 15:10 ? reserved. 9:0 sp_ vcend spu current subpicture display vertical end scan line value. ? spu_hivs 15:10 9:0 bits name description 15:10 ? reserved. 9:0 spu_hivs spu current subpicture display highlight vertical start scan line value. ? spu_hive 15:10 9:0 bits name description 15:10 ? reserved. 9:0 spu_hive spu current subpicture display highlight vertical end scan line value. ? spu_hihs 15:10 9:0 bits name description 15:10 ? reserved. 9:0 spu_hihs spu current subpicture display highlight horizontal pixel start value. ? spu_hihe 15:10 9:0 bits name description 15:10 ? reserved. 9:0 spu_hihe spu current subpicture display highlight horizontal pixel end value. ? spu_hstart 15:10 9:0 bits name description 15:10 ? reserved. 9:0 spu_ hstart spu current subpicture display highlight horizontal pixel change start value.
ess technology, inc. sam0400-103101 37 es6008/18/28/38 data sheet registers preliminary sp_vtctl (0x20001760h, r/w) this register is the subpicture display video timing control register. after reset, it is initialized to 0x0000. spu contrast index registers this section describes the contrast index registers in the spu decoder. sp_con0 (0x200017b0h, r/w) sp_con0 through sp_con9 are registers containing the contrast index for a particular region and pixel type. sp_con0 is the default subpicture display start contrast region register. after reset, it is initialized to 0x0000h.the register bit tables for all these registers are identical to the one shown above. sp_con1:8 (0x200017b4h ? 0x200017d0h, r/w sp_con0 through sp_con9 are registers containing the contrast index for a particular region and pixel type. sp_con1 through sp_con8 are the change region registers. after reset, each register is initialized to 0x0000h. the register bit tables for all of these registers are identical to the one shown above. sp_con9 (0x200017d4h, r/w) sp_con0 through sp_con9 are registers containing the contrast index for a particular region and pixel type. sp_con9 is the highlight region register. after reset, it is initialized to 0x0000h. the register bit tables for all these registers are identical to the one shown above. spu color index registers this section describes the color index registers in the spu decoder. sp_col0 (0x20001780h, r/w) sp_col0 through sp_col9 are registers containing color index for a particular region and pixel type. col0 is the default subpicture display start color region register. after reset, it is initialized to 0x0000h. the register bit tables for all these registers are identical to the one shown above. numchg cindex cs cc par seen rlen chg val id hi val id 15:12 11:8 7:4 3 2 1 0 bits name description 15:12 numchg number of changes in current horizontal stripe. 11:8 cindex code index (current region index). 7:4 cs current state of col/con state machine (read only). 3 ccpa_ seen 1 = start parsing col/con data (one clock cycle) (need to set after risc decodes). 0 = otherwise. 2 rlen 1 = current pixel in subpicture display area. 0 = otherwise. 1 chg val id 1 = current pixel is within a change region (i.e., not default subpicture color/contrast). 0 = otherwise. 0 hi val id 1 = current pixel is within the highlight region. 0 = otherwise. dcba 15:12 11:8 7:4 3:0 bits name description 15:12 d contrast index for emphasis 2 pixel (type 11). 11:0 c contrast index for emphasis 1 pixel (type 10). 7:4 b contrast index for pattern pixel (type 01). 3:0 a contrast index for background pixel (type 00). dc ba 15:12 11:8 7:4 3:0 bits name description 15:12 d contrast index for emphasis 2 pixel (type 11). 11:0 c contrast index for emphasis 1 pixel (type 10). 7:4 b contrast index for pattern pixel (type 01). 3:0 a contrast index for background pixel (type 00). dc b a 15:12 11:8 7:4 3:0 bits name description 15:12 d contrast index for emphasis 2 pixel (type 11). 11:0 c contrast index for emphasis 1 pixel (type 10). 7:4 b contrast index for pattern pixel (type 01). 3:0 a contrast index for background pixel (type 00). dc ba 15:12 11:8 7:4 3:0 bits name description 15:12 d color index for emphasis 2 pixel (type 11). 11:0 c color index for emphasis 1 pixel (type 10). 7:4 b color index for pattern pixel (type 01). 3:0 a color index for background pixel (type 00).
38 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary sp_col1:8 (0x20001784h ? 0x20017a0h, r/w) sp_col0 through sp_col9 are registers containing color index for a particular region and pixel type. sp_ col1:8 are the change region 1-8 registers. after reset, each register is initialized to 0x0000. note : the register bit tables for all of these registers are identical to the one shown above. sp_col9 (0x200017a4h, r/w) sp_col0 through sp_col9 are registers containing color index for a particular region and pixel type. sp_col9 is the highlight region register. after reset, it is initialized to 0x0000. note : the register bit tables for all these registers are identical to the one shown above. host interface (risc side) registers the following describes the host interface risc side registers. r_hostdmaport (0x20003000h, r/w) this register contains data transferred to/from the host (dma port). after reset, it is initialized to 0x0000. r_hostvcxport (0x20003004h, r/w) this register contains data transferred to/from the host (vcx port). after reset, it is initialized to 0x00. r_hostdbgport (0x20003008h, r/w) this register contains data transferred to/from the host (debug port). after reset, it is initialized to 0x00. r_hostmask (0x20003010h, r/w) this register contains the mask bits for interrupts from the host to the risc. after reset, it is initialized to 0x0. r_hostirqstat (0x20003014h, r) this register reads the status of interrupts from the host to the risc; 1=irq, 0=no irq. dcba 15:12 11:8 7:4 3:0 bits name description 15:12 d contrast index for emphasis 2 pixel (type 11). 11:0 c contrast index for emphasis 1 pixel (type 10). 7:4 b contrast index for pattern pixel (type 01). 3:0 a contrast index for background pixel (type 00). dcba 15:12 11:8 7:4 3:0 bits name description 15:12 d[3:0] color index for emphasis 2 pixel (type 11). 11:0 c[3:0] color index for emphasis 1 pixel (type 10). 7:4 b[3:0] color index for pattern pixel (type 01). 3:0 a[3:0] color index for background pixel (type 00). (risc side) host interface dma port 15:0 (risc side) host interface command port 7:0 (risc side) host interface debug port 7:0 endnsel dbgdw dbgtre dmadw dmatre vcxidw vcxitre h2rirq 76543210 bits name description 7 endn _sel big/little endian select 1 = switch upper/lower bytes when write r_hostdmaport. 6:0 mask bits for interrupts from the host to the risc. ? dci err dci irq r2h irq dbg tre dbg dw dma tre dma dw vcxi tre vcxi dw h2r irq 15:109876543210 bits name description 15:10 ? reserved. 9 dcierr dci sector error detect. 1 = previous sector has error. 8 dciirq sector-end interrupt from dci port to risc. 7 r2hirq interrupt flag set by the risc as a signal to the host. 6dbg tre debug transmit register empty (ok for risc to send data to the host). 5 dbgdw debug data waiting (risc needs to read data from the host). 4dma tre dma transmit register empty (ok for risc to send data to the host). 3dma dw dma data waiting (risc needs to read data from the host). 2vcxi tre vcxi transmit register empty (ok for risc to send data to the host). 1vcxi dw vcxi data waiting (risc needs to read data from the host). 0 h2rirq interrupt flag set by the host as a signal to the risc.
ess technology, inc. sam0400-103101 39 es6008/18/28/38 data sheet registers preliminary r_idedat (0x20003018h, r/w) this register contains data sent/received to/from atapi slave, in master mode. after reset, it is initialized to 0x0000h. r_ideaddr (0x2000301ch, r/w) this register contains address sent to atapi slave, in master mode. after reset, it is initialized to 0x0. r_idectl (0x20003020h, r/w) after reset, it is initialized to 0x0000h. r_idesstat (0x20003024h, w) r_idecnt (0x20003028h, r/w) after reset, it is initialized to 0x07ffh. ide_data 15:0 ? ide_addr 7:3 2:0 ? clrirq ide2xpt idest iderst idemsk1 15:13 12 11 10 9 8 idemsk0 idecs hstmode ide_en ide_rw pio mode 76543 2:0 bits name description 15:13 ? reserved. 12 clrirq write 1 to clear sector-end interrupt from atapi slave. 11 ide2 xpt in master mode, write 1 to this bit to enable data transfer from atapi data port to risc. data transfer will continue on until this bit is reset to 0. 10 idest write 1 to signal the beginning of the sector. the sector start signal will be reset by the first data valid. 9 iderst write 1 to reset the atapi slave, then write 0 to unreset. the atapi slave will also be reset at the same time with the es4427. 8ide msk1 mask sector-end interrupt from atapi to risc. 7ide msk0 mask interrupt from atapi to risc. 6 idecs ide chip select 1 = assert cs3fxb. 0 = assert cs1fxb. 5hst mode 0 = slave mode. host will receive commands or data from dvd-dsp. 1 = master mode. host will send read/write commands (comply to atapi). 4 ideen enable the host to write/read to/from the atapi slave. 3 iderw 1 = read from atapi slave. 0 = write to atapi slave. 2:0 pio mode [2:0] pio mode select [2:0]. ? ideirq ide16 ideval 7:3 2 1 0 bits name description 7:3 - reserved. 2 ideirq 1 = sector-end interrupt from atapi slave to risc. 1 ide16 read only bit 1 = 16-bit transfer. if reading from atapi slave, all 16-bit data of r_idedat are valid. if writing to atapi slave, all 16-bit data of r_idedat are received at the atapi slave. 0 = 8-bit transfer. if reading from atapi slave, only the last 8 bits of r_idedat are valid. if writing to atapi slave, only the last 8 bits of r_idedat are received at the atapi slave. 0 ideval 1 = pio cycle is completed. in read mode, read from r_idedat to retrieve the data from the atapi slave; write 1 to clear this bit. ? ide cnt 15:12 11:0 bits name description 15:12 reserved. 11:0 idecnt in master/dci mode, program this register to the sector size. in master mode, reading from this register will reveal the count down value. bits name description
40 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary r_dcictl (0x2000302ch, r/w) this register controls the host port when the vibratto is in dci mode. after reset, it is initialized to 0x000h. host interface (risc-sram interface) registers the section describes the risc-sram interface registers. riface_width (0x20004000h, r/w) this register contains the width of the bus to external memory, and controls the internal cache. the value of the tdmdx pin is sampled at the rising edge of reset# and the riface_width register is programmed according to the bit settings of the following table. ? iormsk acklvl reqlvl syncnum synclvl delay ldr_sel 31:12 11 10 9 8 7 6:2 1:0 bits name description 31:12 reserved. 11 iormsk i/o ready mask enable. 1 =mask i/o ready (default). 0 = don ? t mask. 10 acklvl acknowledge level. 1 = ack level active-high. 0 = ack level active-low. 9 reqlvl request level. 1 = original and delayed sector starts. 0 = original sector start. 8 sync num sync number. 1 = original and delayed sector starts. 0 = original sector start 7 sync lvl sync level. 1 = sync level active-high. 0 = sync level active-low. 6:2 del[4:0] delay sector start cycles. 1:0 ldrsel loader select [1:0] ldr sel1 ldr sel0 description 0 0 bypass mode. 0 1 sanyo loader 1 0 takaya loader. 1 1 sgs-thomson loader. ? dbgmode cachefls cache disable div2:0 b3w b2w b1w b0w 15:11 10 9 8 7:5 4 3 2 1:0 tdmdx/rsel selection 08-bit rom. 116-bit rom. bits name description 15:11 ? reserved. 10 dbgmode debug mode: 0 = save power from outside pins tog- gling. 1 = riscaddr and riscbus are seen from the sram address/data. resets to 1. 9 cache_fls cache flush: 1 = flush. resets to 1. 8 cache disable cache disable signal: 0 = cache enabled. 1 = cache bypassed. resets to 1 (cache disabled). 7:5 div[2:0] clock divisor. 4 b3w bank 3 width 1 = 16 bits wide. 0 = 8 bits wide (default). 3 b2w bank 2 width 1 = 16 bits wide. 0 = 8 bits wide (default). 2 b1w bank 1 width 1 = 16 bits wide. 0 = 8 bits wide (default). 1:0 b0w bank 0 width [1:0] 00 = 8-bit wide (default). 01 = 16-bit wide. 10 = map bank 0 to dram. 11 = undefined.
ess technology, inc. sam0400-103101 41 es6008/18/28/38 data sheet registers preliminary .riface_wait_state (0x20004004h, r/w) this register contains the number of external wait states (from 1 to 32) per access for banks 0-3. the table below gives the hexadecimal value for the number of wait states: riface_aux1 (0x2000402ch, r/w) this register is a general i/o port for interfacing with external devices. when this register is read, the values read are the values at the pin. the two open collector pins allow i 2 c bus communication and require an external pull-up resistor. the default value is for p3:p2 to be tri-state, and p1:p0 to be disabled (i.e., p1, p0 = high (logic 1), and t3, t2 = low (logic 0)). riface_aux2 (0x20004030h, r/w) this register is a second general-purpose i/o port with four tri-state channels. when this register is read, the values read are the values at the pin. default values for tri-state controls are 0 (tri- state) at reset. aux7_is_stall flag operation: the ess risc can be stalled externally via the aux7 port. to configure this port, the aux7_is_stall flag must be set in the riface_aux2 register (this flag defaults to 0). when set, the aux7 (p7) pin loses its aux pin functionality, and becomes the risc stall# pin. stall# is asserted active-low, prior to the rising edge of dci_clk. the ess risc will be stalled the next cycle. . for busy-holdoff operations where the ess risc is accessing a microprocessor which is not ready yet, the external device cannot be accessed during a zero wait state condition, since there is a 1-cycle latency before the stall can take effect. bus controller (video processor) registers this section describes the video processor registers of the bus controller module in detail. buscon_vp_control (0x20008000h, r/w) ? bank3 bank2 bank1 bank0 31:20 19:15 14:10 9:5 4:0 hex value wait state hex value wait state hex value wait state hex value wait state 1f 1 17 9 0f 17 07 25 1e2 16100e180626 1d3 15110d190527 1c4 14120c200428 1b5 13130b210329 1a6 12140a220230 197 111509230131 188 101608240032 (default) ? 0t3t2p3p2p1p0 15:10 9:6 5 4 3 2 1 0 bits name description 15:10 ? reserved. 9:6 ? reserved. always 0. 5:4 t3,t2 tri-state controls. 1 = i/o state selected. 0 = tri-state selected. 3 p3 tri-stateable pin. 2 p2 tri-stateable pin. 1 p1 open collector pin. 0 p0 open collector pin. ? aux7_is_stall t p 15:9 8 7:4 3:0 bits name description 15:9 ? reserved. 8 aux7_is_ stall risc cycle stall. 7:4 t tri-stateable controls. 3:0 p tri-stateable pads. ? dve_108 load_vp vp_rst# 15:3 2 1 0 bits name description 15:3 ? reserved. 2 dve_108 video pll frequency select. 1 = 108 mhz frequency selected. 0 = 54 mhz frequency selected (default). clk80 aux 7 (stall) asserted here stall riscess access here riscess will resume here
42 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary buscon_vp_status (0x20008004h, r) bus controller (memory controller) registers this section describes the memory controller registers of the bus controller module in detail. buscon_dram_control (0x20008100h, r/w) this is the configuration register for the reference memory. after reset, it is initialized to 0x0000. 1 load_vp load vision processor microcode. 1 = load microcode. 0 vp_rst# vision processor reset. 1 = enabled. 0 = reset. ? seq trd iosm cmdq_st 15:5 432 1:0 bits name description 15:5 ? reserved. 4 seq sequencer status. 3 trd transfer ready status. 2 iosm i/o state machine status. 1:0 cmdq _st command queue status. ? sel sclken sd64m sd8 bit big edo sd cf sref en ref en ? ras pre ras del spd edo 31:17 16 15 14 13 12:11 10 9 8:6 5:4 3:2 1:0 bits name description 31:17 ? reserved. 16 sel sclk en sdram clock enable. 1 = pin 70 is sdsclken 0 = pin 70 is doe# 15 sd64m sdram type select. 1 = use 64 mb sdram 0 = use 16 mb sdram bits name description 14 sd8 bit sdram 8-bit select. 1 = sdram is x 8. 0 = sdram is x 16. 13 big edo edo dram select. 1 = edo is 1m x 16 0 = edo is 256k x 16 12:11 sdcf sdram/edo memory configuration. 10 sref en sdram refresh enable. 1 = refresh logic for sdram enabled. 9ref en edo refresh enable. 1 = refresh logic for edo dram enabled. 8:6 ? reserved. 5:4 ras pre ras precharge time control for edo. 3:2 ras del ras to cas delay time. 1:0 spd edo edo dram speed select. bits name description size (mb) sd 64m sd8 bit sd cfg1 sd cfg0 memory configuration 2.0 0 0 0 1 1 pc: 512kx16x2 (16 mb) 4.0 0 0 0 0 2 pc: 512kx16x2 (16 mb) 4.0 0 1 0 1 2 pc: 1mx8x2 (16 mb) 8.0 0 1 0 0 4 pc: 1mx8x2 (16 mb) 8.0 1 0 x x 1 pc: 1mx16x4 (64 mb) 16.0 1 0 x x 2 pc: 1mx16x4 (64 mb) 16.0 1 1 x x 2 pc: 2mx8x4 (64 mb) 16.0 1 1 x x 1 pc: 2mx16x4 (128 mb)
ess technology, inc. sam0400-103101 43 es6008/18/28/38 data sheet registers preliminary buscon_dram_sreftime (0x20008114h, r/w) this register controls the sdram refresh period for the system, and contains the refresh interval value. after reset, it is not initialized. bus controller (command queue) registers this section describes the command queue registers of the bus controller module in detail. buscon_cmdque_ vpdmasetup (0x20008200h, w) the buscon_cmdque_vpdmasetup register takes the video processor dma access requests directed to the command queue and prioritizes the dma requests. audio registers audio interface registers this section describes all the registers controlling the audio section, and serves as a reference for both hardware and firmware engineers who need to understand the internal workings of the vibratto. audioctl (0x2000d008h, r/w) this audio control register enables the corresponding functions and clocks. after reset, it is initialized to 0x00. intval 7:0 bits name description 7:0 intval sdram refresh interval value. ? bk dir hint dws db wx dws dely delx 31:25 24 23 22 20 19 18 17:16 15:9 8:0 bits name description 31:25 ? reserved. 23 bk break. when set, this bit sends the break# signal to the vp at the end of a line. 23 dir data transfer direction. 1 = memory to vp. 0 = vp to memory. 22 hint vp hint block. when set, this bit blocks the dma arbitration to the extent that the next vp dma request will be granted over requests at the same level or below the cur- rent request level for a back-to-back vp dma transaction. 20 dws select dma width enable. 1 = dma width select feature enabled. 0 = disabled. 19 db double dma width select. 1 = double dma width selected. 0 = single dma width selected. 18 wx select delta x as dma width register. 1 = use dma width register. 0 = use delx as dma width register. 17:16 dsel dma width register select. this 2-bit field permits the selection of up to one of eight possible dma width registers, depending on the dma width selected by db bit (bit 19) of this register. four single dma width registers and four double dma width regis- ters are available to support the desired dmas for the memory configuration imple- mented in the design. 15:9 dely transfer y longwords 8:0 delx transfer x scan lines. aien ams aren axen aben dm srst ? 76543210 bits name description 7 aien audio interrupt enable. the corresponding port must be enabled for proper interrupt status. 0 = disabled. 1 = enabled. 6 ams audio master clock selection: 0 = external mclk. 1 = internal mclk. 5 aren audio receive enable. 0 = disabled. 1 = enabled. 4 axen audio transmit enable. the dma must be started before enabling the transmit port. 1 = audio transmit enabled. 0 = audio transmit disabled. 3 aben audio bit clock generator enable (used only when internal mclk is selected). 2 dm data input (either from pri_bus or risc) debug mode: 0 = data from pri_bus. 1 = data from risc_bus. 1 srst soft reset, this bit will self-reset when a ? 1 ? is written. 0 ? reserved.
44 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary audioxmt (0x2000d00ch, r/w) this audio transmit format register is used for setting up the format for the transmit port. after reset, the register is initialized to 0x0000. audiorcv (0x2000d010h, r/w) this is the audio receive format register. after reset, it is initialized to 0x0000. audioapllm (0x2000d014h, r/w) this register is the analog pll frequency divider register. after reset, it is initialized to 0x4ah. tlsb tdge tdfs tdm tcf tfm itfs tbcs am tbcf 15 14 13 12:10 9:8 7:6 5 4 3:2 1:0 bits name description 15 tlsb transmit lsb select. 1 = lsb first. 0 = msb first. 14 tdge transmit bit clock edge select. 1 = output data on falling edge of clock. 0 = output data on rising edge of clock. 13 tdfs transmit data frame sequence select. 1 = last bit sent on last cycle. 0 = first bit sent on first cycle. 12:10 tdm transmit data frame mode select. 000 = 16-bit data frame. 001 = 18-bit data frame. 010 = 20-bit data frame. 011 = 24-bit data frame. 100 = 32-bit data frame. 101 = reserved. 110 = reserved. 111 = reserved. 9:8 tcf transmit cycle frame. 00 = 16-bit cycle frame. 01 = 24-bit cycle frame. 10 = 32-bit cycle frame. 11 = reserved. 7:6 tfm transmit frame mode 00 = normal mode. 01 = left justified mode. 10 = right justified mode. 11 = reserved. 5 itfs inverse audio transmit frame sync. 1 = enabled. 0 = disabled. 4 tbcs audio bit clock select 1 = use internal bit clock and output bit clock. 0 = use external bit clock. 3:2 am audio mode select 00 = stereo l-r channel. 01 = dolby ? digital (5.1 channel). 10 = mpeg-2 audio (7.1 channel). 11 = reserved. 1:0 tbcf audio transmit bit clock frequency select 00 = mclk/8. 01 = mclk/4. 10 = mclk/2. 11 = mclk/16. rlsb rdge rdfs ? rdm rcf rfm rfs rbcs ? rbcf 15 14 13 12 11:10 9:8 7:6 5 4 3:2 1:0 bits name description 15 rlsb receive lsb select. 1 = lsb first. 0 = msb first. 14 rdge receive data bit clock edge select. 1 = input data sampled on falling edge 0 = input data sampled on rising edge. 13 rdfs receive data frame sequence. 1 = last bit sent on last cycle 0 = first bit sent on first cycle. 11:10 rdm receive data frame select 00 = 16-bit data frame. 01 = reserved. 10 = reserved. 11 = reserved. 9:8 rcf receive cycle frame select 00 = 16-bit cycle frame. 01 = 24-bit cycle frame. 10 = reserved. 11 = reserved. 7:6 rfm receive frame mode select. 00 = normal mode. 01 = left justified mode. 10 = right justified mode. 11 = reserved. 5 irfs inverse receive frame sync select. 1 = enabled. 0 = disabled. 4 rbcs receive bit clock select. 1 = use internal bit clock and output bit clock to pin. 0 = use external bit clock. 3:2 ? reserved. 1:0 rbcf receive bit clock frequency select 00 = mclk/8. 01 = mclk/4. 10 = mclk/2. 11 = mclk/1. m 7:0
ess technology, inc. sam0400-103101 45 es6008/18/28/38 data sheet registers preliminary audioaplln (0x2000d018h, r/w) this register is the analog pll frequency multiplier register. after reset, it is initialized to 0x1fh. s/pdif interface registers the following describes the s/pdif interface registers. spdif_ctl (0x2000d01ch, r/w) after reset, it is initialized to 0x00. spdif_csd1:6 (0x2000d020h:0x2000d034h, r/w) this register is the spdif channel status 1 register. after reset, it is initialized to 0x0000 0000. audioimask (0x2000d038h, r/w) this register is the audio interrupt mask register. after reset, it is initialized to 0x00. write a ? 1 ? to the corresponding bit to mask the interrupt. tdm interface registers tdmdata (0x2000e000h, r/w) the tdm data register functions as a container for 16-bit data i/o transfers over the tdm port. bits name description 7:0 m audio frequency divider m. fs od m8 n 765 4:0 bits name description 7 fs sampling frequency select. 1 = 384 sample frequency selected. 0 = 256 sample frequency selected. 6 od output divider. 5 m8 bit 8 of m divider value. 4:0 n audio frequency multiplier n. ? spdif_rst spdif_clk spdif_sfrmv sfrmdb 0 spdif_oe 76 5:4 3 2 1 0 bits name description 7 ? reserved. 6 spdif rst s/pdif soft reset. 5:4 spdif _clk s/pdif bit clock frequency select [1:0]. 00 = spmclk/8 (n=8) 01 = spmclk/4 (n=2) 10 = spmclk/2 (n=4) 11 = spmclk/16 (n=16) 3 spdif sfrmv s/pdif subframe validity select. 2sfrm _db user data bit for subframe. 1 ? reserved. always 0. 0 b0 spdif output enable: 1 = enabled. 0 = disabled. cds1:6 31:0 bits name description 31:0 cds1:6 spdif channel status data. msse mscse mstre msue macs maue matre madw 76543210 bits name description 7 msse mask for spdif channel swap error. 6 mscse mask for spdif channel status empty. 5 mstre mask for spdif transmit register empty. 4 msue mask for spdif underflow error. 3 macs mask for audio channel swap error. 2 maue mask for audio underflow error. 1 matre mask for audio transmit register empty. 0 madw mask for audio data waiting interrupt. tdm data 15:0 bits name description 15:0 tdm data tdm data transferred to and from the tdm port.
46 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet registers preliminary tdmxmtdelay (0x2000e004h, r/w) this register allows a variable delay from the start of frame sync to the start of valid data (for data transmitted from risc to tdm). tdmrcvdelay (0x2000e008h, r/w) this register allows a variable delay from the start of frame sync to the start of valid data (for data transmitted from tdm to risc). ? xmtdelay xmt_phase delay 7:4 3:1 0 bits name description 7:4 ? reserved. 3:1 xmt delay transmit delay value in milliseconds. 0xmt phase delay transmit phase delay. 1 = normal operation. 0 = invalid. ? rcv delay rcv phase delay 7:4 3:1 0 bits name description 7:4 ? reserved. 3:1 rcv delay receive delay value in milliseconds. 0rcv phase delay receive phase delay. 1 = normal operation. 0 = invalid.
ess technology, inc. sam0400-103101 47 es6008/18/28/38 data sheet sdram read and write timing diagrams preliminary sdram read and write timing diagrams figure 14 sdram random column read timing t0 t ck3 dsck dsc[1:0] dras# dcas# dwe# dma[11] t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 raw raw raz caw cax ray raz caz aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 hi-z dma[10] dma[9:0] dqm db[15:0] activate command bank a read command bank a read command bank a read command bank a read command bank a activate command bank a precharge command bank a burst length = 4, dcas# latency = 3
48 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet sdram read and write timing diagrams preliminary figure 15 sdram random column write timing t0 t ck3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rbw rbw rbz cbw cbx rby rbz cbz dbx0 dbx1 dby0 dby1 dby2 dby3 hi-z activate command bank b read command bank b read command bank b read command bank b read command bank b activate command bank b precharge command bank b burst length = 4, dcas# latency = 3 dbw0 dbw3 dbw1 dbw2 dbz1 dbz0 dsck dsc[1:0] dras# dcas# dwe# dma[11] dma[10] dma[9:0] dqm db[15:0]
ess technology, inc. sam0400-103101 49 es6008/18/28/38 data sheet sdram read and write timing diagrams preliminary figure 16 sdram random row read timing t0 t ck3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rbx rbx rby cbx rax cax rby cbyz bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 hi-z activate command bank b read command bank b read command bank a precharge command bank a read command bank b activate command bank b burst length = 8, dcas# latency = 3 rax t rcd t rp t ac3 bx0 ax3 ax4 ax5 ax6 axy by0 precharge command bank b activate command bank a dsck dsc[1:0] dras# dcas# dwe# dma[11] dma[10] dma[9:0] dqm db[15:0]
50 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet sdram read and write timing diagrams preliminary figure 17 sdram random row write timing burst length = 8, cas latency = 3 clk cke cs i/o ras cas we a 11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a 0 - a9 t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank b rbx rbx activate command bank a ray ray day3 t dpl cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t dpl t rcd activate command bank a rax rax
ess technology, inc. sam0400-103101 51 es6008/18/28/38 data sheet sdram read and write timing diagrams preliminary notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time, and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. notes: 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1 ns, (tr/2-0.5) ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1 ns, transient time compensation should be considered, that is, [(tr + tf)/2 - 1] ns should be added to the parameter. table 16 sdram interface timing parameter symbol min. max. unit note row active to row active delay t rrd (min) 18 ns 1 dras# to dcas# delay t rcd (min) 24 ns 1 row precharge time t rp (min) 24 ns 1 row active time t ras (min) 54 ns 1 t ras (max) 100 s row cycle time t rc (min) 90 ns 1 last data in to new column address delay t cdl (min) 1clk2 last data in to row precharge t rdl (min) 1clk2 last data in to burst stop t bdl (min) 1clk2 column address to column address delay t ccd (min) 1clk3 number of valid output data (cas latency =3) 2 ea 4 table 17 operating ac characteristics parameter (cas latency = 3) symbol min. max. unit note clk cycle time t cc 9ns1 clk to valid output delay t sac 7ns1, 2 output data hold time t oh 2.5 ns 2 clk high pulse width t ch 3ns3 clk low pulse width t cl 3ns3 input setup time t ss 2ns3 input hold time t sh 0.5 ns 3 clk to output in low-z t slz 1ns2 clk to output in hi-z t shz 7ns
52 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet sram interface timing preliminary sram interface timing figure 18 sram read timing la[21:0] lcs[3:0]# lwrxx# loe# ld[15:0] address address address t sram_at rd0 rd1 rd0 t sram_at t bs_dt t rc_dstdl t rc_dhtdl t rc_dstdl t rc_dhtdl n waitstate bank select n waitstate symbol parameter min typ max units t dram_ioss dram interface output signal skew 0 3 ns t rc_dstdl read cycle data setup time to data latch 6 ? ns t rc_dhtdl read cycle data hold time to data latch 2 ? ns t sram_at sram access time 2* 33 internal cpu clock cycle t bs_dt bank select delay time 0 3 internal cpu clock cycle
ess technology, inc. sam0400-103101 53 es6008/18/28/38 data sheet sram interface timing preliminary figure 19 sram write timing la[21:0] lcs[3:0]# lwrxx# loe# ld[15:0] address address address t sram_at t sram_at t bs_dt data data data t a_stws t w_stwl t a_htws t a_stws t a_htws symbol parameter min typ max units t sram_ioss sram interface output signal skew 0 3 ns t sram_at sram access time 2* 33 internal cpu clock cycle t bs_dt bank select delay time 0 3 internal cpu clock cycle t a_stws address setup time to write strobe 0.5 0.5 internal cpu clock cycle t a_htws address hold time to write strobe 0.5 0.5 internal cpu clock cycle t w_stwl write strobe pulse width low 1 31.5 internal cpu clock cycle
54 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet tdm interface timing preliminary tdm interface timing figure 20 tdm interface timing tdmclk tdmfs tdmdr tdmtsc# tdmdx 1 0234567 1 0234567 recv channel 1 recv channel 0 t tdm_rd t tdmclk_p transmit channel 0 t tdm_td t tdm#_cod t tdmdr_st t tdmfs_ht t tdmdr_st t tdmdr_ht t tdmdx_dod symbol parameter min typ max units t tdmclk_p tdm clock period 62.5 ? ns t tdm#_cod tdmtsc# control output delay to tdmclk 0 2 t tdmfs_st tdmfs setup time to tdmclk 4 ? t tdmfs_ht tdmfs hold time to tdmclk 2 ? t tdmdr_st tdmdr data setup time to tdmclk 4 ? t tdmdr_ht tdmdr data hold time to tdmclk 2 ? t tdmdx_dod tdmdx data output delay to tdmclk 0 2 t tdm_rd tdm receive delay to tdmfs 0 8 internal cpu clock cycle t tdm_td tdm transmit delay to tdmfs 0 8 internal cpu clock cycle
ess technology, inc. sam0400-103101 55 es6008/18/28/38 data sheet host interface timing preliminary host interface timing note : hdreq# is defined as a minimum value. figure 21 host bus read timing ha[2:0] hd[15:0] hwrite# hread# hwrreq# hrdreq# hirq t hihr#_od t hrdhr#_od t hr# pwl t hr#_pwh t hdhr#_st t hdhr#_ht t hdhr#_ht t hahr#_st t hdrq_ph symbol parameter min typ max units t hahr#_st ha to hread# setup time 4 ? ns t hahr#_ht ha to hread# hold time 2 ? ns t hdhr#_st hd to hread# setup time 0 4 ns t hdhr#_ht hd to hread# hold time 2 ? ns t hr#_pwh hread# pulse width high 30 ? ns t hr# pwl hread# pulse width low 30 ? ns t hrdhr#_od hrdreq# to hread# output delay 0 8 ns t hihr#_od hirq to hread# output delay 0 8 ns t hdrq_ph hdreq# pulse width high (see note) 75 ns
56 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet host interface timing preliminary note : hwrreq# is defined as a minimum value. figure 22 host bus write timing t hahw#_ht t hdhw#_ht t hdhw#_st t hw#_pwl t hw#_pwh ha[2:0] hd[15:0] hwrite# hread# hwrreq# hrdreq# hirq t hihw#_od t hwr#_od t hahw#_st t hwrq_ph symbol parameter min typ max unit t hahw#_st ha to hwrite# setup time 4 ? ns t hahw#_ht ha to hwrite# hold time 2 ? ns t hdhw#_st hd to hwrite# setup time 4 ? ns t hdhw#_ht hd to hwrite# hold time 2 ? ns t hw#_pwl hwrite# pulse width low 30 ? ns t hw#_pwh hwrite# pulse width high 30 ? ns t hwr#_od hwrreq# to hwrite# output delay 0 8 ns t hihw#_od hirq to hwrite# output delay 0 8 ns t hwrq_ph hwrreq# pulse width high (see note) 75 ns
ess technology, inc. sam0400-103101 57 es6008/18/28/38 data sheet dci timing preliminary dci timing figure 23 dci interface timing t ck t reqs t reqd t dackfd t dackrd t errfd , t errrd t syncfd t syncrd t sdtd (wait) (wait) (empty) di-2062 di-2063 dj-0000 dj-0001 dj-0002 dj-0003 edc sector-id dci_clk dci_req# dci_ack# dci_err# dci_fds# dci symbol parameter min typ max units t ck cstrobe output frequency 3.375 mhz t reqs request setup time 100 ns t reqh request hold time 0 ns t dackrd dack rising edge delay 0 5 ns t dackfd dack falling edge delay 0 5 ns t errrd error rising edge delay 0 5 ns t errfd error falling edge delay 0 5 ns t syncrd sync rising edge delay 0 5 ns t syncfd sync falling edge delay 0 5 ns t sdtd sdt[7:0] delay time 0 5 ns
58 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet audio transmit and receive timing diagrams preliminary audio transmit and receive timing diagrams figure 24 right justified mode / 16-bit cycle frame / 16-bit data frame / msb first figure 25 right justified mode / 24-bit cycle frame / 16-bit data frame / msb first figure 26 right justified mode / 32-bit cycle frame / 24-bit data frame / lsb first tbck/ tws/ tsd[3:0]/ 01 15 14 0 15 1 rbck rws rsd 01 15 14 15 14 10 0 15 14 tbck/ tws/ tsd[3:0]/ 01 rbck rws rsd 923 22 1 0 23 22 15 14 1 0 1 0 80 1 tws/ rsd rws rbck 0 tsd[3:0]/ tbck/ 89 1 30 0 31 0 30 31 1 2223 2223 0
ess technology, inc. sam0400-103101 59 es6008/18/28/38 data sheet audio transmit and receive timing diagrams preliminary figure 27 left justified mode / 32-bit cycle frame / 24-bit data frame / msb first figure 28 i 2 s mode tbck/ tws/ tsd[3:0]/ 01 rbck rws rsd 23 22 0 31 30 1 0 31 30 23 22 1 0 23 22 23 tbck/ tws/ tsd[3:0]/ 1 rbck rws rsd 23 2 22 24 23 1 0 31 2 0 31 1 0 23 22 0
60 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet video timing diagrams preliminary video timing diagrams figure 29 ntsc timing figure 30 pal timing 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313
ess technology, inc. sam0400-103101 61 es6008/18/28/38 data sheet video timing diagrams preliminary figure 31 ntsc closed captioning timing figure 32 pal teletext / vertical blanking interval timing 12.91 s s t a r t p a r i t y p a r i t y d0?d6 d0?d6 10.003 s 33.764 s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clockrun-in) two 7-bit + parity ascii characters (data) 27.382 s byte 0 byte 1 10.50.25 s address & data run-in clock teletext vbi line 45 bytes (360 bits) C pal
62 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet video timing diagrams preliminary figure 33 line 21 preamble address codes (same as fcc part 15.119) p reamble a ddress c odes row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 row 9 row 10 row 11 row 12 row 13 row 14 row 15 first byte of code pair: data channel 1 ................................................................ 11 11 12 12 15 15 16 16 17 17 10 13 13 14 14 data channel 2 ................................................................ 19 19 1a 1a 1d 1d 1e 1e 1f 1f 18 1b 1b 1c 1c second byte of code pair: white ................................................................................ 40 60 40 60 40 60 40 60 40 60 40 40 60 40 60 white underline ............................................................... 41 61 41 61 41 61 41 61 41 61 41 41 61 41 61 green ............................................................................... 42 62 42 62 42 62 42 62 42 62 42 42 62 42 62 green underline ............................................................... 43 63 43 63 43 63 43 63 43 63 43 43 63 43 63 blue .................................................................................. 44 64 44 64 44 64 44 64 44 64 44 44 64 44 64 blue underline ................................................................. 45 65 45 65 45 65 45 65 45 65 45 45 65 45 65 cyan ................................................................................. 46 66 46 66 46 66 46 66 46 66 46 46 66 46 66 cyan underline ................................................................ 47 67 47 67 47 67 47 67 47 67 47 47 67 47 67 red ................................................................................... 48 68 48 68 48 68 48 68 48 68 48 48 68 48 68 red underline .................................................................. 49 69 49 69 49 69 49 69 49 69 49 49 69 49 69 yellow ............................................................................... 4a 6a 4a 6a 4a 6a 4a 6a 4a 6a 4a 4a 6a 4a 6a yellow underline .............................................................. 4b 6b 4b 6b 4b 6b 4b 6b 4b 6b 4b 4b 68 4b 6b magenta ........................................................................... 4c 6c 4c 6c 4c 6c 4c 6c 4c 6c 4c 4c 6c 4c 6c magenta underline ........................................................... 4d 6d 4d 6d 4d 6d 4d 6d 4d 6d 4d 4d 6d 4d 6d white italics ...................................................................... 4e 6e 4e 6e 4e 6e 4e 6e 4e 6e 4e 4e 6e 4e 6e white italics underline ..................................................... 4f 6f 4f 6f 4f 6f 4f 6f 4f 6f 4f 4f 6f 4f 6f indent 0 ............................................................................ 50 70 50 70 50 70 50 70 50 70 50 50 70 50 70 indent 0 underline ........................................................... 51 71 51 71 51 71 51 71 51 71 51 51 71 51 71 indent 4 ............................................................................ 52 72 52 72 52 72 52 72 52 72 52 52 72 52 72 indent 4 underline ........................................................... 53 73 53 73 53 73 53 73 53 73 53 53 73 53 73 indent 8 ............................................................................ 54 74 54 74 54 74 54 74 54 74 54 54 74 54 74 indent 8 underline ........................................................... 55 75 55 75 55 75 55 75 55 75 55 55 75 55 75 indent 12 .......................................................................... 56 76 56 76 56 76 56 76 56 76 56 56 76 56 76 indent 12 underline ......................................................... 57 77 57 77 57 77 57 77 57 77 57 57 77 57 77 indent 16 .......................................................................... 58 78 58 78 58 78 58 78 58 78 58 58 78 58 78 indent 16 underline ......................................................... 59 79 59 79 59 79 59 79 59 79 59 59 79 59 79 indent 20 .......................................................................... 5a 7a 5a 7a 5a 7a 5a 7a 5a 7a 5a 5a 7a 5a 7a indent 20 underline ......................................................... 5b 7b 5b 7b 5b 7b 5b 7b 5b 7b 5b 5b 7b 5b 7b indent 24 .......................................................................... 5c 7c 5c 7c 5c 7c 5c 7c 5c 7c 5c 5c 7c 5c 7c indent 24 underline ......................................................... 5d 7d 5d 7d 5d 7d 5d 7d 5d 7d 5d 5d 7d 5d 7d indent 28 .......................................................................... 5e 7e 5e 7e 5e 7e 5e 7e 5e 7e 5e 5e 7e 5e 7e indent 28 underline ......................................................... 5f 7f 5f 7f 5f 7f 5f 7f 5f 7f 5f 5f 7f 5f 7f n ote : all indent codes (second byte equals 50h5fh, 70th7fh) assign white as the color attribute.
ess technology, inc. sam0400-103101 63 es6008/18/28/38 data sheet video timing diagrams preliminary figure 34 ntsc composite (vdac) line output waveform figure 35 pal composite (vdac) line output waveform 92.5 ire 30.8 ire 82.7 ire 89.5 ire 100 ire 40 ire 40 ire 7.5 ire ideal white yellow cyan green magenta red blue black (ccir-624-4 scaled to 40 ire sync) dve ntsc sq simulation code v ire 954 1.233 172.7 774 1.001 140.1 715 0.924 129.4 476 0.616 86.2 336 0.434 60.8 263 0.340 47.6 221 0.286 40.0 106 0.138 19.3 83 0.108 15.1 0 0.000 0.0 234mv (32.7 ire) 627mv (87.8 ire) 620mv (86.8 ire) 700mv (98 ire) 300mv (42 ire) 300mv ideal white yellow cyan green magenta red blue black (ccir-624-4 scaled to 300mv sync) dve pal sq simulation code v ire 960 1.241 173.8 774 1.001 140.1 712 0.921 128.9 464 0.600 84.0 349 0.451 63.1 232 0.300 42.0 115 0.149 20.8 46 0.060 8.4 0 0.000 0.0
64 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet video timing diagrams preliminary figure 36 luma (ydac) line output waveform figure 37 chroma (cdac) line output waveform white level 100 ire 7.5 40 ire ideal white yellow cyan green magenta red blue black (ccir-624-4 scaled to 40 ire sync) dve ntsc sq simulation code v ire 387 1.001 140.1 716 0.926 129.6 476 0.615 86.2 322 0.416 58.3 263 0.340 47.6 221 0.286 40.0 0 0.000 0.0 18.0 sync level blank level setup step 100 89.5 72.3 61.8 45.7 35.2 620 0.802 112.2 561 0.725 101.5 417 0.539 75.5 burst level 20 ire 40 ire 20 ire ideal (ccir-624-4 scaled to 40 ire sync) 82.7 ire white yellow cyan green magenta red blue black 117.7 ire 109.3 ire 109.3 ire 82.7 ire 117.7 ire dve ntsc sq simulation code v ire 847 1.095 153.3 826 1.068 149.6 512 0.662 92.7 398 0.514 72.0 273 0.353 49.4 199 0.257 36.0 178 0.230 32.2 626 0.810 113.4 752 0.972 136.1 dve ntsc sq simulation code v ire 847 1.095 153.4 827 1.069 149.7 512 0.662 92.7 273 0.353 49.4 199 0.257 36.0 178 0.231 32.3 752 0.972 136.1
ess technology, inc. sam0400-103101 65 es6008/18/28/38 data sheet video timing diagrams preliminary figure 38 sync and pixel clock timings ntsc pal :line1: :line1: :line2: :line2: :line19: :line23: 122 period 132 period field 1 ntsc pclk2x pclk yuv[7:0] . . . . . . . . . . . . . . . . . . . . . . . . pal :line 263: :line 313: :line 264: :line 314: :line 281: :line 336: 122 period 132 period vsync# hsync# . . . . . . . . field 2 . . . . . . . . . . yuv[7:0] cr0 pclk2x pclk . . . . . . . . . . . . . . . . . . . . . . . . vsync# hsync# . . . . . . . . . . . . . . 3 lines/ntsc 2.5 lines/pal cb0 y0 cr1 63.5 period . . . . . . . . . . . . . . . . cr0 cb0 y0 cr1 63.5 period . . . . . . . . . . . . . . . . . . . 1 period = 1 pixel clock
66 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet electrical specifications preliminary electrical specifications absolute maximum ratings recommended operating conditions warning: stress beyond those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. exposure to the absolute maximum ratings conditions for extended periods may affect device reliability. dc electrical characteristics video dac storage temperature range -65 c to 150 c operating temperature range 0 c to 70 c voltage range on any pin -0.5 v to + 0.5 v power dissipation 1.8 w operating temperature range 0 c to 70 c supply voltage vcc 2.80v150 mv; 375 ma nominal supply voltage vee 3.60v150 mv; 50 ma nominal supply voltage avee 3.60v150 mv; 10 ma nominal supply voltage advee 3.60v150 mv; 150 ma nominal parameter condition min typ max unit dac resolution ? 10 ? bits integral linearity (inl) ? 2 2 lsb differential linearity error (dnl) ? 0.5 1 lsb gain error ? -- 5 % dac output impedance ? 20k ? ? output current-dac 33.5 35.2 36.5 ma internal reference voltage (v ref ) 1.17 1.235 1.29 v output load 34 37.5 42 ? output capacitance ?? 40 pf table 18 dc electrical characteristics symbol parameter min max unit comments v ih high-level input voltage 2.0 vcc+0.25 v all inputs ttl levels except clk v il low-level input voltage -0.3 0.8 v all inputs ttl levels except clk v clkh clk high-level input 2.0 vcc+0.25 v ttl level input v clkl clk low-level input -0.3 0.8 v ttl level input v oh high-level output voltage 3.0 ? vi oh = 1 ma v ol low-level output voltage ? 0.45 v i ol = 4 ma i li input leakage current ? 15 a i lo output leakage current ? 15 a c in input capacitance ? 10 pf fc = 1 mhz c o input/output capacitance ? 12 pf fc = 1 mhz c clk clk capacitance ? 20 pf fc = 1 mhz
ess technology, inc. sam0400-103101 67 es6008/18/28/38 data sheet electrical specifications preliminary ac electrical characteristics figure 39 pixel, doubled pixel, tdm and audio master clock timing t1, t6, t11, t16 t2, t7, t12, t17 t3, 18, t13, t18 t4, t9, t14, t19 t5, t10, t15, t20 clock table 19 clock timing parameters symbol parameter min typ max units pixel clock timing t1 t clk_p clock period 30 100 ns t2 t clk_lt clock low time 24 ? ns t3 t clk_ht clock high time 24 ? ns t4 t clk_rt clock rise time ? 6ns t5 t clk_ft clock fall time ? 6ns t6 t pclk_p pixel clock period 33 ? ns doubled pixel clock timing t7 t pclk_lt pixel clock low time 15 ? ns t8 t pclk_ht pixel clock high time 15 ? ns t9 t pclk_rt pixel clock rise time ? 4ns t10 t pclk_ft pixel clock fall time ? 4ns audio master clock timing t11 t aclk_p audio clock period 54 ? ns t12 t aclk_lt audio clock low time 21 ? ns t13 t aclk_ht audio clock high time 21 ? ns t14 t aclk_rt audio clock rise time ? 6ns t15 t aclk_ft audio clock fall time ? 6ns tdm clock timing t16 t tdmclk_p tdm clock period 62.5 ? ns t17 t tdmclk_lt tdm clock low time 25 ? ns t18 t tdmclk_ht tdm clock high time 25 ? ns t19 t tdmclk_rt tdm clock rise time ? 6ns t20 t tdmclk_ft tdm clock fall time ? 6ns
68 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet es60x8 design guide preliminary es60x8 design guide dvd printed circuit board layout guidelines about multilayer boards a multilayer board with dedicated power and ground planes is recommended. the power and ground planes should be placed close together in order to increase the distributed mutual capacitance on the board. distributing the mutual capacitance will result in the board exhibiting less crosstalk and less power supply noise, while also providing better high frequency bypass characteristics. a good ground net should have low impedance and low inductance, as poor grounding can cause the loss of the low-level dc noise margin. noise spikes due to long ground return paths are also possible. these noise spikes can cause false switching of sensitive strobe signals. in some cases, the fast switching may show up as being software dependent because different combinations of 1 ? s and 0 ? s create different return currents in the ground net. the power net, like the ground net, should be low impedance and low inductance. a high impedance power net may cause large voltage drops, reducing the high-level noise margin. multilayer boards exhibit less emi problems because of the low inductance planes. the planes reduce the size of the current loop, thus reducing the radiation area. solid power and ground planes will help dissipate heat from devices such as voltage regulators and the vibratto, resulting in the heat becoming redirected towards cooler areas of the board. this dissipating effect can be realized even if the device is not electrically connected to the net. power and ground planes the ground planes should encompass all the ground pins, voltage reference circuitry, and power traces for the vibratto, along with the analog output and digital signal traces leading to the vibratto. both the analog and digital sections of the vibratto should have their own dedicated power planes, so as to reduce the possibility of plane-to- plane noise coupling. digital signal interconnect the digital signal inputs to the vibratto should be isolated as much as possible from the from the analog outputs and other analog output circuitry. as the vibratto implements high clock rates, avoid long clock lines to preclude noise pickup. finally, active termination resistors that may be implemented for the digital inputs should be connected to the regular pcb power plane whenever possible. analog signal interconnect the analog outputs should be isolated from the digital signals as much as possible since they are susceptible to crosstalk from the digital lines. digital traces must not be run adjacent to or under analog lines. the distance between the analog output pin and the output connector should be kept short as possible to minimize noise pickup and reflections caused by impedance mismatch. the load resistor for each output should be placed as close to the pin as possible to minimize reflections. the analog output signals should overlay the ground plane and not the power plane in order to maximize the high frequency power supply rejection. layout considerations all of the vibratto dvd processors require heat sinking. to accomplish this in an economical manner, use the following pcb layout shown in figure 40. the land pattern for the vibratto still uses the standard 208 pin pqfp footprint. figure 40 pcb layout considerations addition of a solid copper fill on the top and bottom layers, along with 2mm square solder mask exposures and via holes in the center of each exposure is recommended. if a multilayer board is used, the power and ground planes will act as a heat spreader, precluding the need for copper fill on the top and bottom layers. power supply decoupling for peak performance, all bypass capacitors should be placed as close as possible to the device using the shortest leads possible. chip capacitors are recommended for their low lead inductance. surface mount capacitors should be placed on the component side to reduce the inductance caused by vias. if vias must be used, the vias should be as large as possible to minimize inductance effects. a typical implementation uses 0.1 f capacitors for high-frequency noise rejection, and a 10 f to 47 f capacitor for low- 208 pin pqfp land pattern solid copper (top & bottom layers) 2mm 2mm 2mm 2mm vi a solid copper with solder mask solid copper without solder mask 4mm 4mm
ess technology, inc. sam0400-103101 69 es6008/18/28/38 data sheet es60x8 design guide preliminary frequency ripple. to further reduce power supply ripple, place a larger capacitor, such as a 47 f to 470 f capacitor, near the power supply entry point. compensation capacitor decoupling comp pin 109 must be decoupled to the advee supply using a surface mount 0.1 f ceramic capacitor. a surface mount capacitor is recommended because of its low lead inductance. lead inductance reduces the ability of the circuit to reject noise. the capacitor should be placed on the component side, as close as possible to the comp pin 109 using a short, wide trace. reference voltage decoupling vref pin 107 is used to decouple the internal voltage reference for the video dac. decouple the pin with a 0.1 f ceramic capacitor to the ground plane. place the capacitor as close as possible to vref pin 107 and connect the capacitor using a short, wide trace. dac current adjustment resistor rset pin 110 is used to select the full scale output current of the internal video dac. a resistor between 200 and 1000 ohms should connect between rset pin 110 and the ground plane, depending on whether or not buffer circuitry is implemented in the board design. the resistor must be placed close to the pin and connected using a short, wide trace. figure 41 typical video dac connection diagram sdram signal routing the sdram signals should be routed on the component layer if possible using the shortest trace possible. the use of vias should be kept to a minimum to reduce reflections due to discontinuities in the signal path. when routing the sdram clock signal, care should be taken. this clock signal operates at the same frequency as the decoder. additional air gap between the clock signal and other signals is recommend to reduce crosstalk. about the vibratto evaluation board the evaluation mainboard is provided as an example of how the vibratto dvd processor can be implemented in a dvd player design. a dvd player design can not be fully implemented using only one board. additional boards such as a/v output, mic preamp and front panel boards are also needed. the design was done in a modular fashion so that customer-specific configurations could also be realized with this design. evaluation mainboard features the vibratto evaluation mainboard supports the following features: playback of cd, vcd, svcd, dvd, mp3, kodak picture cd, jpeg format disc media analog 2-channel audio output digital 6-channel audio output s/pdif output 2-channel analog audio input built-in video encoder supporting interlace and 480-pixel progressive scan outputs interface to vfd front control panel interface for infra-red remote control direct connection to atapi dvd loader supports mod x loader modules supports mod x-flash memory module boards that can be directly connected to this board include those listed in table 20: advee comp vref rset 111 109 107 110 0.1 f 200 ? 1000 ? 0.1 f vibratto table 20 add-on dvd player boards and modules board name description ess dvd vfd control front panel for dvd applications, vfd display, mic preamp. ess avatar 6 channel dolby digital output, s/pdif optical and coax output, video filters mod x - flash flash/sram development module mod x - flash socket socketed tsop flash develop- ment module mod x - philips philips loader interface module mod x - thomson thomson loader interface module mod x - sony sony loader interface module mod x - dci/sanyo dci/sanyo loader interface module mod x - ude/panasonic ude/panasonic loader interface module
70 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet es60x8 design guide preliminary the vibratto evaluation board has been designed to use the atapi interface and internal video encoder features of the device. all of the vibratto dvd processors can operate at a variety of frequencies. refer to table 21 to set the operating frequency. the internal video encoder supports four combinations of video outputs. the outputs can be in ntsc or pal formats. when the internal video encoder of the vibratto is used, pin 109 becomes the compensation input, pin 107 is the bypass pin for the internal voltage reference, and pin 110 sets the full scale output current of the dacs. table 22 lists the possible video output combinations for the vibratto. connector pin assignments table 23 through table 33 list the jumper pins on the asteroid dvd demo board and the corresponding signal names. table 21 the vibratto clock frequency matrix sel_pll2 sel_pll1 sel_pll0 multiplier 000vco off 0011x 0 1 0 bypass 0112x 1004.5x 1013x 1103.5x 1114x table 22 video output combinations matrix mode ydac pin 113 udac pin 106 vdac pin 114 cdac pin 108 ay ccompc bycompcompc cy ucompv dy u c v table 23 js1 (dvd drive expansion connector pin signal pin signal 1 +5v 2 +12v 3 vcc33 4 +12v 5rst# 6 ld9 7 ld8 8 ld11 9 ld10 10 ispclk 11 ld12 12 demclk 13 hwrq# 14 rd1 15 wr2 16 tdmdr 17 tdmclk 18 tdmfs 19 aux0 20 aux1 21 aux3 22 aux5 23 gnd 24 gnd table 24 js2 atapi interface connector pin signal pin signal 1 reset 2 gnd 3 dd15 4 d0 5 dd14 6 d1 7 dd13 8 d2 9 dd12 10 d3 11 dd11 12 d4 13 dd10 14 d5 15 dd9 16 d6 17 dd8 18 d7 19 gnd 20 key 21 drq 22 gnd 23 iow# 24 gnd 25 ior# 26 gnd 27 iochrdy 28 bale 29 dack# 30 gnd 31 irq14 32 iocs16# 33 a1 34 reserved 35 a0 36 a2 37 cs0# 38 cs1# 39 activity 40 gnd table 25 js3 video connector pin signal name pin signal name 1 udac 2 cdac 3ydac4 gnd 5vdac6 gnd 7 vsync# 8 hsync# table 23 js1 (dvd drive expansion connector pin signal pin signal
ess technology, inc. sam0400-103101 71 es6008/18/28/38 data sheet es60x8 design guide preliminary table 26 js4 power connector pin signal name pin signal name 1+5v2gnd 3gnd4+12v 5-12v6gnd table 27 js5 vfd interface connector pin signal name pin signal name 1+5v2 ir 3 gnd 4 vfd_clk 5 vfd_cs 6 vfd_data table 28 js6 s/pdif connector pin signal name pin signal name 1txp2gnd 3gnd4 txn table 29 js7 audio input connector pin signal name pin signal name 1micr2 gnd 3gnd4micl table 30 js8 audio output connector pin signal name pin signal name 1zeror 2 right 3 gnd 4 gnd 5left 6zerol table 31 js9 audio board connector pin signal name pin signal name 1 clkex 2 gnd 3tbck 4tsd0 5tws 6tsd1 7gnd 8tsd2 9 aux3 10 gnd 11 aux5 12 karclk# 13 eaux32 14 karcs# 15 rst# 16 kardin# 17 nc 18 kardout# 19 gnd 20 nc 21 nc 22 nc 23 rsd 24 tsd3 25 rbck 26 rws table 32 js10 sram interface connector pin signal name pin signal name 1la19 2la18 3la16 4la17 5la15 6la14 7la12 8la13 9la7 10la8 11 la6 12 la9 13 la5 14 la11 15 la4 16 loe# 17 la3 18 la10 19 la2 20 lcs3# 21 la1 22 ld7 23 la0 24 ld6 25 gnd 26 ld5 table 33 js11 eprom/rom emulator interface connector pin signal name pin signal name 1 +5v 2 vcc33 3la21 4la20 5ld15 6ld14 7ld13 8ld12 9 ld11 10 ld10 11 ld9 12 ld8 13 ld0 14 wrll# 15 ld1 16 wrhl# 17 ld2 18 lcs0# 19 ld3 20 lcs2# 21 ld4 22 rst# 23 gnd 24 gnd table 31 js9 audio board connector pin signal name pin signal name
72 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet es60x8 design guide preliminary memory interface the evaluation mainboard allows the installation of both an 128-byte eeprom device, an eprom or rom emulator, and 16-, 64- and 128-mbit sdram components. u1 is a 128-byte eeprom, which is used to store user preferences and system settings. u4 and u5 can be used to install either an eprom or a rom emulator. the socket is capable of supporting up to 1mbyte of code. changing r14 or r15 supports either 3.3v or 5.0v devices. install a 0 ohm resistor at r14 for 5.0v devices or at r15 for 3.3v devices. all of the vibratto dvd processors support 16mbit, 64mbit and 128mbit sdram components. the evaluation mainboard is designed for 64mbit or 128mbit sdram parts. the pinout for 64mbit and 128mbit sdram parts are identical, allowing either type of module to be installed on the board. reset u12 is a maxim max823 microprocessor supervisor. the part generates a 200 ms active-low reset signal after the supply rail has reached the internal threshold voltage. the active-low reset signal then directly connects to the vibratto. the max823 also supports a manual reset feature. shorting and opening jp1 will initiate a reset signal that is active for 200ms. the manual reset can also be activated through the rom emulator. external sram/flash connectors connectors js10 and js11 are used for connecting additional memory or i/o devices to the vibratto, such as the mod x-flash module. the signals on the connectors are the risc processor interface signals, and are the same signals that go the eprom or rom emulator socket. memory spaces corresponding to banks 0, 2 and 3 are supported. if the system is to boot from memory connected to these connectors, the memory must be configured to respond to bank 3 memory space while memory in u4 (eprom/rom emulator) is configured for a different bank or disabled. an example is booting from a mod x-flash module. the module would need to be configured for bank 3 while socket u4 is left empty. if the mod x-flash module was being programmed, then the module could be configured for memory bank 2 while the rom emulator in u4 is configured for bank 3. the vibratto always boots from the highest address of bank 3, so the system must be designed accordingly. bank 0 is reserved for sram only. if sram is not used, bank 0 must be left unconnected. audio pll u8 is an optional pll that can be used to generate the master audio clock for the dac, adc and the vibratto. the parts can be programmed to generate a variety of frequencies. the following frequencies used by the audio pll are listed in table 34. audio input analog audio is input to the vibratto evaluation mainboard through js7. the maximum input level is 1vrms (0db). the analog audio is converted into digital form by a pcm1800 adc from texas instruments/burr-brown. the pcm1800 is a 20-bit, 2-channel device capable of sampling rates up to 48khz. both master and slave modes are supported by the pcm1800, but on the evaluation board, the pcm1800 has been configured for master mode operation. master mode was selected so that the audio receive port on the vibratto could be run at a different sample rate from the audio transmit port. additional adcs can be tested using connector js9. video, vfd and s/pdif the vibratto evaluation mainboard has been configured to use the internal video encoder. the analog video and the horizontal and vertical sync signals are output on js3. a back-end board having 75ohm termination, video filtering, esd protection, and the appropriate connectors are needed to correctly interface to a tv. at this time, only the vdac output has the termination and filtering implemented on the same circuit board as the vibratto. this was done as an example of how a simple filtering circuit could be designed. js5 is used to connect a front panel to the vibratto evaluation mainboard. infrared input is supported along with any vacuum fluorescent display (vfd) controller supporting a 3-wire interface. the infrared input should be a demodulated ttl-level signal. power (+5v) is also provided on the connector for the vfd controller, but the filament voltage for the display must be supplied externally. table 34 u8 audio pll sampling frequencies sampling rate (khz) 256fs (mhz) 384fs (mhz) 192fs (mhz) 32.0 8.192 12.288 n/a 44.1 11.2896 16.9344 n/a 48.0 12.288 18.432 n/a 64.0 16.384 24.576 n/a 88.2 22.5792 33.6688 n/a 96.0 24.576 36.864 n/a 192.0 n/a n/a 36.864
ess technology, inc. sam0400-103101 73 es6008/18/28/38 data sheet es60x8 design guide preliminary the s/pdif output from the vibratto is a ttl-level digital signal. connector js6 is used to output the s/pdif signal. this signal is must be sent to a line driver circuit before being sent to an external decoder. about the dvd-audio daughterboard the dvd-audio daughterboard is designed to demonstrate the 6-channel dvd-audio features and karaoke features of the vibratto dvd processor. the daughterboard inputs 6-channel digital audio from an ess dvd decoder board and converts it into 6 channels of dolby digital-compliant analog audio. included on the demo board is a yamaha yss903 for karaoke processing, s/pdif output circuit, and an anti-aliasing filter for ntsc or pal video. daughterboard features the dvd-audio daughterboard supports the following features: dolby digital compliant 6 channels of 24-bit audio at a maximum sampling rate of 96 khz 2 channels of 24-bit audio at a maximum sampling rate of 192 khz supports akm ak4356 or wolfson wm8736 audio dacs karaoke processing with yamaha yss903 cd-da audio bypass option coax and optical s/pdif output ntsc/pal video output rf modulator output option composite video output s-video output component (yuv) video output rgb video output functional description the dvd-audio daughterboard is designed to meet all the requirements of the dolby digital simplified configuration. audio is sent from the dvd decoder main board to the daughterboard through js2. from js2, the audio is sent in digital form to either an akm ak4356 or a wolfson wm8736 audio dac for digital-to- analog conversion. the analog audio from the audio dac is sent through several filters for anti-aliasing and bass redirection, as required by the dolby digital specifications. figure 42 identifies the available high-pass and low-pass filter configurations. output at the rca connector is 2.0 v rms . figure 42 high-pass and low-pass filter configurations included on the daughterboard is a yamaha yss903 karaoke processor. microphone input is through js1. the output of the yss903 is summed with the front left and front right channels from the audio dac. programming and control of the yss903 is done from the dvd decoder mainboard. to control the yss903 karaoke device on the daughterboard, u9, u10 and u11 were added to the board as additional logic. u9 is used as a decoder on the risc bus. the output of u9 is used to clock data into latch u11, which drives the signals for the yss903, and an onboard pll. u10 is a tri-state buffer that drives data from the yss903 on to the risc bus. two of the decoder outputs of u9 are routed to the js1 dvd drive expansion connector for use by external devices. depending on the number of i/os and type of logic used in the design, a decoder may not be needed. this design used memory bank 1 for i/o, but bank 2 is also usable for the same purpose. banks 0 and 3 are not recommended for this purpose because of memory addressing issues. js1 p5 p2/p3 tv video out avatar dvd-audio and karaoke daughterboard p1 24-bit karaoke ic karaoke in/mic in 6-channel dvd-audio out js8 video filters dvd decoder home receiver/amplifier s/pdif js2 audio in video in audio dac js6 power
74 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet es60x8 design guide preliminary figure 43 is the daughterboard block diagram. figure 43 daughterboard block diagram figure 44 is a diagram showing all the connections on the avatar board, including pinouts for connectors p1 and p5. figure 44 daughterboard connectors for dvd drives that output cd-da audio only in analog form, the daughterboard includes an option for cd-da bypass. the cdda audio is fed into js3 where it is amplified by +6-db before being passed through a selector/switch circuit. the +6 db gain can be changed based on the output of the specific drive. the expected amplitude of the cdda audio is 1v rms . s/pdif is input to the daughterboard through js4 as a ttl-level signal. the ttl-level signal is sent to an rs- 422 driver and an optical transmitter. the output of the rs-422 driver is galvanically isolated in accordance with iec958 specifications (unbalanced line), and then sent to connector p2 for output. the output of p2 is 500 mv p-p , when measured across a 75-ohm resistor connected at the output. the video signal from the ess dvd decoder board is input on js8. this signal passes through a passive anti-aliasing low-pass filter before being output on p4 and p5. the video signals are arranged to provide representative combinations of video output options, including composite, s-video, component, and rgb. the exact output of the various connectors will vary, depending on the version of the dvd decoder mainboard being used. an option for and rf modulator output is included on the daughterboard. refer to the description for jp1 for more details. jumpers jumper jp1 is used to select if the second composite video output is to be directed to an rca connector or an rf modulator module. connecting pins 1 and 2 will select the rca connector while connecting pins 2 and 3 will select the rf modulator. table 35 summarizes the jumper settings for jp1. connector pin assignments table 36 through table 42 list the connectors on the daughterboard and the corresponding signal names. a a b b c c d d e e 4 4 3 3 2 2 1 1 lpf lpf audio dac lpf lpf lpf hpf hpf hpf front right front left center left surround right surround lfe lpf b l o c k d i a g r a m o f a v a t a r b o a r d yamaha yss903 mic interface to dvd decoder board audio output left right fl fr c ls rs lfe mute mute control mute mute mute mute mute +6db switch cdda input s/pdif output rs422 driver galvanic isolation coax optical optical transmitter anti-aliasing low pass filter (x4) composite component s-video rgb 2nd-order, 40khz cutoff, butterworth low pass filter, g=1.825 lpf 1st-order, 120hz cutoff unity-gain high pass filter hpf k e y video output a a b b c c d d e e 4 4 3 3 2 2 1 1 p5 js8 js7 jp1 js6 js5 js2 js1 js3 js4 p4 p3 p2 p1 main power host interface powerdown reset output mic input video input rf modulator output s/pdif input cdda bypass input s-video output s/pdif output (optical) s/pdif output (coax) 6-channel analog audio output video output p1 pinout - audio fl fr c lfe rs ls u/b comp #1 y/g v/r p5 pinout - video comp #2 nc table 35 jp1 jumper settings jp1 ? position signal name 1 and 2 rca connector 2 and 3 rf modulator table 36 js1 mic input pin signal name pin signal name 1mic2gnd
ess technology, inc. sam0400-103101 75 es6008/18/28/38 data sheet es60x8 design guide preliminary table 37 js2 dvd decoder interface pin signal name pin signal name 1 audclk 14 karcs# 2 gnd 15 extrst# 3 tbck 16 kardin 4 tsda 17 pwrdn 5 tws 18 kardout 6 tsdb 19 gnd 7 gnd 20 cdfix 8 tsdc 21 smute 9 cntla 22 nc 10 gnd 23 nc 11 cntlb 24 nc 12 karclk# 25 nc 13 cntlc 26 nc table 38 js4 s/pdif input interface pin signal name pin signal name 1 left 3 gnd 2 gnd 4 right table 39 js5 reset/powerdown pin signal name pin signal name 1 reset/ pwrdn 2 gnd table 40 js6 daughterboard power connector pin signal name pin signal name 1 vcc (+5v) 4 +12v 2gnd 5 ? 12v 3gnd 6 nc table 41 js7 coax modulator output pin signal name pin signal name 1 composite 2 gnd table 42 js8 video input pin signal name pin signal name 1 cvbs1 4 chroma 2gnd 5 nc 3 luma 6 cvbs2
76 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix a: mainboard reference design schematics preliminary appendix a: mainboard reference design schematics figure 45 es60x8 device interface es60xx pll0 pll1 pll2 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1 pll2 pll1 pll0 1 0 1 0 0 0 1 1 mult vco off 4.5x 4.0x 2.0x bypass 3.0x 1.0x 3.5x pll3 rsel ydac udac vdac cdac y c comp c comp comp c c y y y comp u u v v a b c d mode 8-bit rom video dac power pll power 16-bit rom ld14 ld3 lcs3# ld6 loe# wrhl# ld13 ld11 ld5 ld15 ld4 ld8 cpuclk ld9 lcs2# ld7 ld1 wrll# ld12 ld10 ld0 lcs1# ld2 rst# la20 la18 la14 la1 la3 la19 la0 la10 la21 la12 la16 la8 la13 la5 la9 la17 la4 la7 la2 la15 la6 la11 ha0 hcs3# hrd# hd11 hd8 hd12 ha1 hirq hwr# hd4 hd3 hd15 hd13 hiordy hd7 hcs1# hrst# hd9 hd6 hd14 hd1 hd2 ha2 hd0 hd5 hd10 hiocs16# hsync mclk pclk2x vsync tsd0 tws eaux32 spdif tsd1 dcs0# dras0# dcas# dbank0 dbank1 dwe# dqm dcke db0 db8 db4 db1 dma9 dma5 db2 db5 dma4 dma3 dma10 dma8 dma6 dsck db13 db9 dma7 dma11 dma2 dma1 db10 dma0 db12 db6 db11 db7 db3 tdmdx tsd0 tsd1 tws tbck tsd2 tsd3 spdif tdmdx vref udac vref cdac comp rset ydac vdac comp rset tdmdr aux1 aux0 lcs0# eaux40 hwdq# rws rbck rsd xin ld[0..7] ld[8..15] cpuclk loe# wrll# lcs2# wrhl# lcs3# lcs1# rst# la[0..21] ha[0..2] hd[0..15] hiordy hwr# hrd# hrst# hirq hcs3# hiocs16# hcs1# eaux32 tsd0 tws hsync vsync mclk pclk2x tbck dcs0# dras0# dbank0 dbank1 dcas# dwe# dqm dcke db[0..15] dma[0..11] dsck aux5 aux0 aux4 aux7 aux6 aux1 aux2 aux3 tsd1 tsd2 tsd3 udac cdac ydac vdac tdmdr tdmfs spdif lcs0# hwrq# eaux40 rbck rws rsd xin xout vdd vcc33 avee advee advee vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 advee avee vcc33 r38 r37 c13 open r42 4.7k r25 open (4.7k) r43 4.7k r26 open (4.7k) r41 open (4.7k) r24 4.7k r23 4.7k r27 4.7k c47 0.1uf c38 0.1uf r39 274 ohm 1% u1 at24c01-10tc-2.7 s0 1 s1 2 s2 3 gnd 4 sda 5 scl 6 wc 7 vcc 8 l6 nfm2012p 1 3 2 l7 nfm2012p 1 3 2 c74 0.1uf c75 10uf c32 10uf c37 0.1uf r40 open (4.7k) u2 es60xx vcc 9 vee 1 vcc 35 hd0/dci[0]/eaux1[0] 122 vcc 83 vee 18 vcc 121 dcs0 100 vcc 44 vcc 139 vee 27 vcc 172 hd1/dci[1]/eaux1[1] 123 vee 59 yuv0/camyuv2/udac 106 vee 68 hd2/dci[2]/eaux1[2] 124 vee 75 vee 92 hd3/dci[3]/eaux1[3] 125 vee 99 yuv1/vref 107 vee 104 hd4/dci[4]/eaux1[4] 126 vee 130 vee 148 hd5/dci[5]/eaux1[5] 127 vee 157 yuv2/cdac 108 vee 159 hd6/dci[6]/eaux1[6] 128 vee 164 vee 183 hd7/dci[7]/eaux1[7] 131 vee 193 yuv3/comp 109 vee 201 hd8/dci_fds/eaux2[0] 132 advee 111 hd9/eaux2[1] 133 yuv4/rset 110 hd10/eaux2[2] 134 hd11/eaux2[3] 135 yuv5/ydac 113 hd12/eaux2[4] 136 hd13/eaux2[5] 137 yuv6/vdac 114 hd14/eaux2[6] 140 hd15/eaux2[7] 141 yuv7camyuv3 115 avee 51 vss 129 dma0 53 la4 2 dma1 54 dma2 55 la5 3 dma3 56 la6 4 dma4 57 la7 5 dma5 58 la8 6 la9 7 vss 8 la10 10 la11 11 la12 12 la13 13 la14 14 la15 15 la16 16 vss 17 la17 19 la18 20 la19 21 la20 22 la21 23 reset 24 tdmdx/rsel 25 vss 26 tdmdr 28 tdmclk 29 tdmfs 30 tdmtsc 31 tws/sel_pll2 32 tsd0/sel_pll0 33 vss 34 tsd1/sel_pll1 36 tsd2 37 tsd3 38 mclk 39 tbck 40 spdif/sel_pll3 41 nc/camvs 42 vss 43 rsd 45 rws 46 rbck 47 nc/apll xin 49 xout 50 vss 52 vss 60 dma6 61 dma7 62 dma8 63 dma9 64 dma10 65 dma11 66 vss 67 dcas 69 dcke/doe 70 dwe 71 dras0 72 dbank0/dras1 73 dbank1/dras2 74 vss 76 db0 77 db1 78 db2 79 db3 80 db4 81 db5 82 vss 84 db6 85 db7 86 db8 87 db9 88 db10 89 db11 90 vss 91 db12 93 94 db14 db15 96 dcs1 97 vss 98 dqm 101 dsck 102 vss 103 clk 105 vss 112 pclk2xscn/camyuv4 116 pclkqscn/camyuv5/aux3[2] 117 vsscn/camyuv6eaux3[1] 118 hsscn/camyuv7/eaux3[0] 119 vss 120 vss 138 hwrq/dci_req/eaux4[1] 142 hrdq/eaux4[0] 143 hirq/dci_err/eaux4[7] 144 hrst/eaux3[5] 145 hiordy/eaux3[3] 146 vss 147 hwr/dci_clk/eaux4[5] 149 hrd/dci_ack/eaux4[6] 150 hiocs16/campclk/eaux3[4] 151 hcs1fx/eaux3[7] 152 hcs3fx/eaux3[6] 153 ha0/eaux4[2] 154 ha1/eaux4[3] 155 vss 156 ha2/eaux4[4] 158 aux0 160 aux1 161 aux2/iow 162 vss 163 aux3/ior 165 aux4 166 aux5 167 aux6 168 aux7 169 loe 170 vss 171 lcs0 173 lcs1 174 lcs2 175 lcs3 176 vss 177 ld0 178 ld1 179 ld2 180 ld3 181 ld4 182 vss 184 ld5 185 ld6 186 ld7 187 ld8 188 ld9 189 ld10 190 ld11 191 vss 192 ld12 194 ld13 195 ld14 196 ld15 197 lwrll 198 lwrhl 199 vss 200 camyuv0 202 camyuv1 203 la0 204 la1 205 la2 206 la3 207 vss 208 xout tdmclk tdmfs tdmclk aux4 aux3 aux7 aux2 aux6 aux0 aux1 aux5
ess technology, inc. sam0400-103101 77 es6008/18/28/38 data sheet appendix a: mainboard reference design schematics preliminary figure 46 memory interface external sram/flash connectors ext reset 4 5 sot23-5 1 top max823 watchdog enable 2 3 1234 5 6 7 8 top view 4 5 sot23-5 1 top nc7sz125 2 3 ma0 ma1 ma2 ma3 ma6 ma4 ma7 ma5 ma11 ma9 ma10 ma8 cke cs0# ras0# we# cas# dqmx bank0 bank1 mb0 mb1 mb2 mb3 mb4 mb5 mb7 mb6 mb8 mb9 mb11 mb10 mb12 mb13 mb15 mb14 dma0 db0 ras0# cas# we# dqmx cs0# bank1 bank0 wrll# emrst# lcs3# loe# la0 la9 la5 la10 la17 la2 la7 la21 la1 la12 la14 la11 la16 la13 la3 la6 la15 la4 la8 dma1 dma2 dma3 dma4 dma5 dma6 dma7 dma8 dma9 dma10 dma11 ma9 ma11 ma8 ma5 ma7 ma6 ma4 ma0 ma1 ma2 ma3 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 mb4 mb5 mb6 mb7 mb8 mb9 mb10 mb11 mb12 mb13 mb14 mb15 ma10 mb2 mb3 mb1 mb0 la18 la19 cke la20 la6 la3 la7 la5 la16 la4 la12 la15 la19 la0 la2 la1 la14 la13 la8 la9 la11 la17 loe# la18 lcs3# la10 ld5 ld7 ld6 rst# ld1 ld13 ld9 lcs2# ld10 lcs0# wrll# ld8 ld15 ld0 ld11 ld12 la21 ld2 ld14 ld4 la20 wrhl# ld3 lcs1# wr0 rd0 rd1 wr2 fs2 fs1 fs3 fs0 wr0 karcs# kardin karclk# watchdog watchdog rst# ld4 ld2 ld7 ld3 ld5 ld3 ld1 ld0 ld7 ld6 ld0 ld6 ld1 ld5 ld2 ld4 kardout ld7 rd0 la4 la5 wrll# dma[0..11] db[0..15] dras0# dcas# dwe# dqm dcs0# dbank1 dbank0 wrll# emrst# la[0..21] ld[0..7] lcs3# loe# dcke dsck wrhl# lcs0# ld[8..15] lcs1# fs2 fs1 fs0 fs3 rst# emrst# karclk# karcs# kardin kardout wr2 rd1 lcs2# vcc33 vcc33 vccr +5v vcc33 +5v vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 r18 33 ohm r21 33 ohm r19 33 ohm r13 33 ohm r12 33 ohm r16 33 ohm r17 33 ohm u5 rom emulator reset 1 clk/ce1 2 we 3 addr/ce1 4 rn14 10 ohm x 4 1 2 3 4 5 6 7 8 rn13 10 ohm x 4 1 2 3 4 5 6 7 8 rn12 10 ohm x 4 1 2 3 4 5 6 7 8 rn10 10 ohm x 4 1 2 3 4 5 6 7 8 rn9 10 ohm x 4 1 2 3 4 5 6 7 8 rn8 10 ohm x 4 1 2 3 4 5 6 7 8 rn11 10 ohm x 4 1 2 3 4 5 6 7 8 r20 33 ohm c54 10uf c10 0.1uf r14 0 ohm r15 open (0 ohm) u3 64mb sdram vcc 1 dq0 2 dq1 4 vssq 6 dq2 5 dq3 7 vccq 3 dq4 8 dq5 10 vssq 12 dq6 11 dq7 13 vccq 9 dqml 15 we 16 cas 17 ras 18 cs 19 a11 35 a10 22 a0 23 a1 24 a2 25 a3 26 vcc 14 vss 28 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 nc 36 cke 37 clk 38 dqmh 39 nc 40 vccq 43 dq8 42 dq9 44 vssq 46 dq10 45 dq11 47 vccq 49 dq12 48 dq13 50 vssq 52 dq14 51 dq15 53 vss 41 ba0 20 ba1 21 vcc 27 vss 54 c11 15pf r9 33 ohm js10 hdr-13x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 js11 hdr-12x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 u9 74lvx138 q0 15 a0 1 q1 14 a1 2 q2 13 a2 3 q3 12 e0 4 q4 11 e1 5 q5 10 e2 6 q6 9 q7 7 vcc 16 gnd 8 u11 74lvx374 d1 3 d2 4 d3 7 d4 8 d5 13 d6 14 d7 17 d8 18 q1 2 q2 5 q3 6 q4 9 q5 12 q6 15 q7 16 q8 19 clk 11 oe 1 gnd 10 vcc 20 u12 max823reuk-t rst 1 gnd 2 mr 3 vcc 5 wri 4 jp1 hdr-2 1 2 r47 10k r46 2.2k r48 open (0 ohm) u10 nc7sz125 oe 1 a 2 gnd 3 y 4 vcc 5 u4 27c080 d0 13 a0 12 d1 14 a1 11 d2 15 a2 10 d3 17 a3 9 d4 18 a4 8 d5 19 a5 7 d6 20 a6 6 d7 21 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 a16 2 ce 22 oe 24 a18 31 a17 30 a19 1 vcc 32 gnd 16
78 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix a: mainboard reference design schematics preliminary figure 47 atapi interface 6 chan audio adc es60xx ldr demod audio pll audio dac ispclk cpuclk pclk2x fs0 fs1 fs2 fs3 mclk clkex demclk clkad xin xout vcc33 vcc33 vcc33 vcc33 r10 33 ohm r8 open (33 ohm) c9 open (15pf) c36 open (15pf) r7 33 ohm osc1 osc 33.33mhz en 1 gnd 2 out 3 vcc 4 u8 open (cy2907) fs1 1 fs2 2 fs3 3 agnd 4 gnd 5 pd 6 xtalin 7 xtalout 8 oer 9 oea 10 clka 11 vdd 12 refclk 13 fs0 14 y1 open (14.74560mhz) c30 open (18pf) r32 0 ohm r33 33 ohm r34 33 ohm r45 open (33 ohm) r44 open (33 ohm) r31 33 ohm c29 open (18pf) c99 open (15pf) c40 open (15pf) c17 open (15pf) c12 open (15pf) 33 ohm c18 open (15pf) y2 xtal 27mhz c100 27pf c14 27pf r49 100k l9 3.3uh c102 1000pf r11 open (33 ohm) r53 open (33 ohm) atapi interface dvd drive expansion card detect for compact flash audio board connector dirq dd2 dd1 dd8 drst# diocs16# dd13 dd0 dacs1# dd9 dd6 dd14 dd5 dd10 dd15 da0 da1 dd7 dd4 dd11 dd12 dd3 dwr# drd# diordy hd0 ha0 ha1 ha2 hd1 hd2 hd3 hd4 hd5 hd6 hd7 hd8 hd9 hd10 hd11 hd12 hd13 hd14 hd15 da0 da1 da2 dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 drst# ld9 ld11 karclk# kardout kardin karcs# rst# dacs3# da2 ispclk ld8 ld10 ld12 ld13 ld14 ld15 rst# rd1 wr2 dwr# drd# diordy dirq diocs16# dacs1# dacs3# hd[0..15] ha[0..2] hrst# eaux40 hwrq# aux0 aux3 aux1 aux5 tdmdr tdmfs tdmclk tws demclk rbck rws rsd tbck clkex tsd3 tsd0 tsd1 tsd2 ld[8..15] karclk# karcs# kardin kardout aux3 aux5 eaux32 rst# rd1 wr2 hiordy hwr# hrd# hirq hiocs16# hcs1# hcs3# +12v +5v vcc33 vcc33 vcc33 +5v r3 4.7k r2 4.7k js2 hdr-20x2 reset 1 gnd 2 d7 3 d8 4 d6 5 d9 6 d5 7 d10 8 d4 9 d11 10 d3 11 d12 12 d2 13 d13 14 d1 15 d14 16 d0 17 d15 18 gnd 19 key 20 drq 21 gnd 22 iow 23 gnd 24 ior 25 gnd 26 iochrdy 27 bale 28 dack 29 gnd 30 irq14 31 iocs16 32 a1 33 reserved 34 a0 35 a2 36 cs0 37 cs1 38 activity 39 gnd 40 rn4 33 ohm x 4 1 2 3 4 5 6 7 8 rn7 33 ohm x 4 1 2 3 4 5 6 7 8 rn3 33 ohm x 4 1 2 3 4 5 6 7 8 rn6 33 ohm x 4 1 2 3 4 5 6 7 8 rn2 33 ohm x 4 1 2 3 4 5 6 7 8 rn5 47 ohm x 4 1 2 3 4 5 6 7 8 rn1 47 ohm x 4 1 2 3 4 5 6 7 8 r1 0 ohm js9 hdr-13x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 js1 hdr-12x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 l5 nfm2012p 1 3 2 r33 clkda 1011 08.1920 32.7680 fs3:fs0 18.4320 1010 16.3840 1001 22.5792 1101 1100 0001 1110 0110 0101 1111 24.5760 12.2880 18.4320 0011 0000 0100 freq (mhz) 73.7280 49.1520 16.9344 11.2896 0010 1000 0111 36.8640 33.8688 45.1584 67.7376
ess technology, inc. sam0400-103101 79 es6008/18/28/38 data sheet appendix a: mainboard reference design schematics preliminary figure 48 video and audio dacs video right gnd gnd left zeror zerol master mode left justif ied, 20 bit audio in micr gnd micl gnd +5v gnd gnd gnd +12v -12v power vfd-data +5v vfd vfd-cs vfd-clk gnd ir txp gnd gnd txn s/pdif audio out audio adc es60xx osc, reset, ttl, pll sdram audio adc audio dac decoupling capacitors 123 4 top sot-223 123 4 top ddpak bottom 12 3 vdac ydac udac cdac tbck tsd0 tws aux3 aux5 eaux32 clkda rbck rws rsd clkad rst# aux2 aux6 aux7 aux4 spdif vsync hsync va5 vcc33 va5 +5v +12v +5v +5v +5v vdd vcc33 +5v vcc33 vdd vcc33 vcc33 vcc33 va5 +5v va5 vcc33 vdd c5 470pf c6 470pf 2.2uh js3 hdr-8 jst-xh 1 2 3 4 5 6 7 8 r6 75 ohm 1% u7 pcm1742ke bck 1 data 2 lrck 3 dgnd 4 vdd 5 vcc 6 voutl 7 agnd 9 vcom 10 zeror 11 zerol 12 md 13 mc 14 ml 15 sck 16 voutr 8 c19 0.1uf c20 10uf c27 10uf c26 10uf js8 hdr-6 jst-xh 1 2 3 4 5 6 c15 470pf c16 470pf u6 pcm1800 vinl 1 vref1 2 refcom 3 vref2 4 vinr 5 rstb 6 bypas 7 fmt0 8 fmt1 9 mode0 10 mode1 11 fsync 12 lrck 13 bck 14 dout 15 sysclk 16 dgnd 17 vdd 18 cinnr 19 cinpr 20 cinnl 21 cinpl 22 vcc 23 agnd 24 c24 4.7uf c23 4.7uf c22 1uf c25 1uf js7 hdr-4 jst-xh 1 2 3 4 c1 220uf js4 hdr-6 jst-xh 1 2 3 4 5 6 r30 33 ohm r22 4.7k js5 hdr-6 jst-xh 1 2 3 4 5 6 js6 1 2 3 4 r36 33 ohm c28 open reg2 reg1117-adj adj 1 vout 2 vin 3 tab 4 c81 10uf c78 0.1uf c76 100uf r29 365 ohm 1% r28 412 ohm 1% c84 0.1uf c77 10uf c33 10uf reg1 reg1117-3.3 adj 1 vout 2 vin 3 tab 4 c31 100uf c2 0.1uf c7 0.1uf c56 10uf c59 10uf c64 0.1uf c71 0.1uf c67 10uf c51 0.1uf c65 0.1uf c55 0.1uf c43 10uf c68 10uf c45 0.1uf c41 0.1uf c63 0.1uf c21 0.1uf c86 0.1uf c35 0.1uf c39 0.1uf c87 10uf c90 0.1uf c96 10uf c89 0.1uf c8 10uf c91 10uf c72 0.1uf c73 10uf c62 0.1uf c52 0.1uf c53 0.1uf c49 10uf c60 0.1uf c61 10uf c97 10uf c93 0.1uf c94 0.01uf c98 10uf l8 nfm2012p 1 3 2 c85 100uf c95 0.1uf c80 10uf c82 10uf c83 0.01uf c79 0.1uf c92 0.1uf l4 ferb c70 0.1uf c69 10uf c46 10uf c58 0.1uf c57 10uf c66 0.1uf c50 0.1uf c42 0.1uf c44 0.1uf c88 0.1uf c34 100uf c48 10uf r5 open (33 ohm) c4 open (47pf) l2 open (ferb) r4 open (33 ohm) c3 open (47pf) l1 open (ferb) r50 75 ohm 1% r51 75 ohm 1% r52 75 ohm 1%
80 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix b: mainboard bill of materials preliminary appendix b: mainboard bill of materials table 43 bill of materials item qty location description capacitors, smd 1 4 c5, c6, c15, c16 cap, cer, smt, 0805, 470pf, 5%, 50v, npo 2 2 c83, c94 cap, cer, smt, 0805, 0.01 f, 10%, 25v, x7r 3 40 c2, c7, c10, c19, c21, c35, c37, c38, c39, c41, c42, c44, c45, c47, c50, c51, c52, c53, c55, c58, c60, c62, c63, c64, c65, c66, c70, c71, c72, c74, c78, c79, c84, c86, c88, c89, c90, c92, c93, c95 cap, cer, smt, 0805, 0.1 f, 10%, 25v, x7r 4 2 c22, c25 cap, tant, smt, case a, 1 f, 20%, 25v 5 2 c23, c24 cap, tant, smt, case a, 4.7 f, 20%, 16v 6 29 c8, c20, c26, c27, c32, c33, c43, c46, c48, c49, c54, c56, c57, c59, c61, c67, c68, c69, c73, c75, c77, c80, c81, c82, c87, c91, c96, c97, c98 cap, tant, smt, case a, 10 f, 2 0 % , 1 6 v 7 4 c31, c34, c76, c85 cap, tant, smt, case c, 100 f, 20%, 10v capacitors, through hole 8 1 c1 cap, alum, radial, 220 f, 20%, 25v, 2.5mm ls resistors, smd, 5% 9 3 r1, r15, r32 res, smt, 0805, 0 ohm, 5%, 1/10w 10 1 r9 res, smt, 0805, 10 ohm, 5%, 1/10w 11 18 r7, r8, r10, r11, r12, r13, r16, r17, r18, r19, r20, r21, r30, r31, r33, r34, r35, r36 res, smt, 0805, 33 ohm, 5%, 1/10w 12 2 r37, r38 res, smt, 0805, 1k, 5%, 1/10w 13 1 r46 res, smt, 0805, 2.2k, 5%, 1/10w 14 9 r2, r3, r22, r23, r24, r27,r40, r42, r43 res, smt, 0805, 4.7k, 5%, 1/10w 15 1 r47 res, smt, 0805, 10k ohm, 5%, 1/10w resistors, smd, 1% 16 1 r6 res, smt, 0805, 75 ohm, 1%, 1/10w 17 1 r39 res, smt, 0805, 274 ohm, 1%, 1/10w 18 2 r28, r29 res, smt, 0805, 412 ohm, 1%, 1/10w resistor arrays, smd, 5% 19 7 rn8, rn9, rn10, rn11, rn12, rn13, rn14 res, array, 10 ohm, 5%, 1/6w, 4 res, isolated bourns cay16-100j4 20 5 rn2, rn3, rn4, rn6, rn7 res, array, 33 ohm, 5%, 1/6w, 4 res, isolated bourns cay16-330j4 21 2 rn1, rn5 res, array, 47 ohm, 5%, 1/6w, 4 res, isolated bourns cay16-330j4 ferrites, inductors and emi filters 22 1 l4 ferrite bead, 1210 23 1 l3 inductor, 2.2 h, 1210 24 4 l5, l6, l7, l8 emi filter, nfm2012p13c105f, murata, 0805 voltage regulators 25 1 reg2 reg, reg1117-adj, burr-brown, sot-223 26 1 reg1 reg, reg1117-3.3, burr-brown, ddpak
ess technology, inc. sam0400-103101 81 es6008/18/28/38 data sheet appendix b: mainboard bill of materials preliminary headers & connectors 27 1 jp1 header, 2x1, 0.1" centers 28 2 js7,js6 header, 4x1, 0.1" centers, jst-xh 29 3 js4,js5,js8 header, 6x1, 0.1" centers, jst-xh 30 1 js3 header, 8x1, 0.1" centers, jst-xh 31 2 js11,js1 header, 12x2, 0.1" centers 32 2 js10,js9 header, 13x2, 0.1" centers 33 1 js2 header, 20x2, 0.1" centers sockets 34 1 u5 rom emulator 35 1 u4 socket, dip-32, 0.6" oscillators & crystals 36 1 osc1 osc, 27mhz, smt, epson sg-636pce 27.000m2 37 1 y1 crystal, 14.74560mhz, 18pf, hcm-49 ics 38 1 u2 ic, es6038, pqfp-208 39 1 u3 ic, sdram, 64mb, 1mx16x4, 133mhz, 7.5ns, 54 tsop 40 1 u1 ic, eeprom, at24c01-10tc-2.7, so-8, atmel 41 1 u12 ic, reset, max823reuk-t, sot23-5, maxim 42 1 u11 ic, 74lvx374, tssop-20, fairchild 43 1 u9 ic, 74lvx138, tssop-16, fairchild 44 1 u10 ic, nc7sz125, sot23-5, fairchild 45 1 u8 ic, pll, cy2907, cypress, so-14 46 1 u7 ic, audio dac, pcm1742ke, ssop-16, burr- brown 47 1 u6 ic, audio adc, pcm1800, ssop-24, burr-brown table 43 bill of materials (continued) item qty location description
82 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary appendix c: mainboard gerber files figure 49 component layer
ess technology, inc. sam0400-103101 83 es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 50 solder layer
84 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 51 drill template
ess technology, inc. sam0400-103101 85 es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 52 ground plane
86 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 53 power layer
ess technology, inc. sam0400-103101 87 es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 54 solder mask top layer
88 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 55 solder mask bottom layer
ess technology, inc. sam0400-103101 89 es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 56 silkscreen bottom layer
90 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix c: mainboard gerber files preliminary figure 57 silkscreen top layer
ess technology, inc. sam0400-103101 91 es6008/18/28/38 data sheet appendix d: dvd-audio daughterboard schematics preliminary appendix d: dvd-audio daughterboard schematics figure 58 audio and control interface
92 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix d: dvd-audio daughterboard schematics preliminary figure 59 video connectors
ess technology, inc. sam0400-103101 93 es6008/18/28/38 data sheet appendix d: dvd-audio daughterboard schematics preliminary figure 60 karaoke and audio dacs
94 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix d: dvd-audio daughterboard schematics preliminary figure 61 fl and fr filters
ess technology, inc. sam0400-103101 95 es6008/18/28/38 data sheet appendix d: dvd-audio daughterboard schematics preliminary figure 62 c, ls and rs filters
96 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix d: dvd-audio daughterboard schematics preliminary figure 63 lfe filter and cd-da amplifier
ess technology, inc. sam0400-103101 97 es6008/18/28/38 data sheet appendix e: dvd-audio daughterboard bill of materials preliminary appendix e: dvd-audio daughterboard bill of materials table 44 dvd-audio daughterboard bill of materials item qty location description capacitors, smd 1 34 c8, c10, c12, c14, c23, c24, c26, c27, c40, c52, c54, c56, c67, c69, c70, c74, c82, c96, c99, c100, c101, c109, c114, c116, c117, c123, c142, c143, c151, c158, c161, c167, c178, c188 cap, cer, smt, 0805, 0.1 f, 10%, 25v, x7r 2 6 c140, c145, c159, c160, c168, c177 cap, cer, smt, 0805, 0.01 f, 10%, 50v, z5u 3 6 c16, c35, c36, c46, c76, c103 cap, cer, smt, 0805, 3300 pf, 10%, 25v, x7r 4 6 c43, c59, c63, c80, c86, c94 cap, cer, smt, 0805, 22 pf, 5%, 50v, npo 5 4 c163, c172, c175, c183 cap, cer, smt, 0805, 56 pf, 5%, 50v, npo 6 4 c157, c170, c180, c186 cap, cer, smt, 0805, 330 pf, 5%, 50v, npo 7 4 c3, c9, c15, c25 cap, cer, smt, 0805, 100 pf, 5%, 50v, npo 8 2 c97, c98 cap, cer, smt, 0805, 220 pf, 5%, 50v, npo 9 17 c18, c19, c21, c22, c29, c30, c48, c53, c78, c81, c88, c105, c108, c162, c171, c174, c182 cap, cer, smt, 0805, 470 pf, 5%, 50v, npo 10 3 c7, c62, c90 cap, cer, smt, 0805, 2700 pf, 10%, 25v, x7r capacitors, through-hole 11 48 c1, c2, c4, c5, c13, c28, c31, c32, c33, c34, c37, c38, c39, c41, c42, c44, c45, c49, c50, c55, c58, c60, c61, c64, c66, c71, c73, c75, c79, c83, c84, c85, c87, c89, c92, c93, c95, c102, c106, c107, c110, c111, c112, c115, c121, c122, c126, c148 cap, alum, radial, 10 f, 20%, 16v, 2-mm ls 12 3 c173, c181, c184 cap, alum, radial, 470 f, 20%, 25v, 5-mm ls 13 6 c147, c153, c164, c165, c166, c176 cap, alum, radial, 100 f, 20%, 25v, 2.5-mm ls resistors, smd, 5% 14 2 r74, r102 res, smt, 1210, 4.7 ? 5%, 1/4w 15 3 r126, r128, r130 res, smt, 0805, 33 ? 5%, 1/10w 16 16 r112, r113, r114, r115, r116, r117, r118, r120, r121, r122, r123, r124, r125, r127, r129, r133 res, smt, 0805, 75 ? 5%, 1/10w 17 6 r40, r57, r61, r69, r78, r88 res, smt, 0805, 10 ? 5%, 1/10w 18 6 r47, r59, r62, r72, r81, r91 res, smt, 0805, 100k ? 5%, 1/10w 19 1 r149 res, smt, 0805, 4.7k ? 5%, 1/10w 20 1 r93 res, smt, 0805, 18k ? 5%, 1/10w 21 2 r139, r150 res, smt, 0805, 1k ? , 5%, 1/10w 22 1 r83 res, smt, 0805, 560 ? 5%, 1/10w 23 12 r8, r13, r26, r29, r31, r32, r48, r51, r67, r71, r89, r96 res, smt, 0805, 470 ? 5%, 1/10w
98 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix e: dvd-audio daughterboard bill of materials preliminary resistors, smd, 5% (continued) 24 2 r23, r34 res, smt, 0805, 0 ? 5%, 1/10w resistors, smd, 1% 25 23 r1, r2, r5, r6, r7, r10, r12, r14, r16, r19, r25, r30, r35, r37,r38, r39, r44, r53, r63, r70, r84, r86, r95 res, smt, 0805, 10k ? 1%, 1/10w 26 12 r3, r17, r28, r33, r36, r43, r45, r54, r64, r75, r80, r97 res, smt, 0805, 10.5k ? 1%, 1/10w 27 3 r22, r77, r99 res, smt, 0805, 499k ? 1%, 1/10w ferrites and inductors 28 4 fb3, fb5, fb7, fb8 ferrite bead, axial 29 4 l1, l4, l7, l10 inductor, 1 h, axial 30 4 l2, l5, l8, l11 inductor, 2.7 h, axial 31 4 l3, l6, l9, l12 inductor, 0.68 h, axial diodes 32 8 d2, d3, d4, d5, d6, d7, d8, d9 diode, 1n6263, axial transistors and regulators 33 1 u14 reg, 78m05, +5v, to ? 220 34 1 u13 reg, 78m09, +9v, to ? 220 35 1 u15 reg, 79m09, -9v, to ? 220 headers and connectors 36 1 js1 header, 1x2, 0.1-in. centers, jst xhp-2 37 2 js6, js8 header, 1x6, 0.1-in. centers, jst xhp-6 38 1 js4 header, 1x4, 0.1-in. centers, jst xhp-4 39 1 js2 header, 2x10, 0.1-in. centers 40 1 p2 conn, rca, single, rt angle, board mount 41 2 p5,p1 conn, rca, 6 conn, rt angle, bd mount 42 1 p4 conn, s-video, 4-pin min din, rt angle, bd mount ic devices 43 1 u10 ic, yss903, yamaha, so ? 28 44 1 u7 ic, audio dac, ak4356, akm, qfp ? 44 45 7 u1, u2, u3, u4, u5, u8, u9 ic, opamp, dual, opa2134, so ? 8 46 1 u12 ic, ds75176bt, national semi, so ? 8 47 1 u16 ic, ds1233 to ? 92 miscellaneous 48 1 p3 fiber optic transmitter, totx178, toshiba 49 1 t1 transformer, 6-pin, 1:1, schott 67129600 table 44 dvd-audio daughterboard bill of materials (continued) item qty location description
ess technology, inc. sam0400-103101 99 es6008/18/28/38 data sheet appendix f: dvd-audio daughterboard gerber files preliminary appendix f: dvd-audio daughterboard gerber files figure 64 daughterboard silkscreen
100 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix f: dvd-audio daughterboard gerber files preliminary figure 65 daughterboard top layer
ess technology, inc. sam0400-103101 101 es6008/18/28/38 data sheet appendix f: dvd-audio daughterboard gerber files preliminary figure 66 daughterboard bottom layer
102 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix f: dvd-audio daughterboard gerber files preliminary figure 67 daughterboard solder mask top layer
ess technology, inc. sam0400-103101 103 es6008/18/28/38 data sheet appendix f: dvd-audio daughterboard gerber files preliminary figure 68 daughterboard solder mask bottom layer
104 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix f: dvd-audio daughterboard gerber files preliminary figure 69 daughterboard solder paste top layer
ess technology, inc. sam0400-103101 105 es6008/18/28/38 data sheet appendix f: dvd-audio daughterboard gerber files preliminary figure 70 daughterboard drill hole template
106 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix g: vfd bill of materials preliminary appendix g: vfd bill of materials table 45 vfd bill of materials item qty location description capacitors, 0805 smd 1 7 c8, c9, c11, c25, c27, c28, c30 cap, cer, smt, 0805, 0.1 f, 10%, 25v, x7r 2 2 c13, c5 cap, cer, smt, 0805, 150 pf, 5%, 50v, npo capacitors, power 3 6 c3, c4, c10, c12, c15, c18 cap, alum, radial, 1 f, 20%, 25v, 2-mm ls 4 2 c1, c16 cap, alum, radial, 4.7 f, 20%, 25v, 2-mm ls 5 1 c6 cap, alum, radial, 10 f, 20%, 16v, 2-mm ls 6 4 c2, c7, c17, c26 cap, alum, radial, 47 f, 20%, 16v, 2-mm ls 7 1 c29 cap, alum, radial, 47 f, 20%, 35v, 3.5-mm ls 8 1 c14 cap, alum, radial, 22 f, 20%, 16v, 2-mm ls resistors, smd, 5% 9 2 r1, r16 res, smt, 0805, 47 ? , 5%, 1/10w 10 4 r2, r9, r10, r18 res, smt, 0805, 22k ? , 5%, 1/10w 11 2 r3, r17 res, smt, 0805, 2.2k ? , 5%, 1/10w 12 7 r4, r8, r14, r28, r29, r30, r31 res, smt, 0805, 10k ? , 5%, 1/10w 13 2 r5, r15 res, smt, 0805, 220 ? , 5%, 1/10w 14 2 r6, r13 res, smt, 0805, 12k ? , 5%, 1/10w 15 1 r7 res, smt, 0805, 10 ? , 5%, 1/10w 16 1 r32 res, smt, 0805, 56k ? , 5%, 1/10w 17 6 r35, r36, r38, r39, r40, r43 res, smt, 0805, 4.7k ? , 5%, 1/10w potentiometers 18 2 r11, r12 pot, 50k ? ic devices 19 1 u6 ic,vfd cont., nec upd16311, qfp-52 20 1 u7 ic, ir rec, tfms5380 21 1 u1 ic, mic amp, ba7760f, so-14 22 1 u2 ic, cmos, hcf4069u, so-14 display 23 1 u5 fluorescent disp, zec vfd28-0704 diodes 24 9 d1, d2, d5, d6, d7, d8, d9, d10, d11 diode, 1n4148, through-hole transistors 25 2 q1, q2 trans, 2n7002lt1, sot-23 headers and connectors 26 1 jp1 header, 1x2, 0.1-in. centers 27 3 js2, js3, js6 header, 1x4, 0.1-in. centers, jst xhp-4 28 1 js8 header, 1x8, 0.1-in. centers, jst xhp-8
ess technology, inc. sam0400-103101 107 es6008/18/28/38 data sheet appendix g: vfd bill of materials preliminary headers and connectors (continued) 29 2 j1, j2 0.25-in. phone jack switches 30 34 s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, s32, s34, s35 switch, pushbutton, spst un-install components 31 1 s33 switch, toggle, spdt, digikey (ckn1071-nd) 32 5 d12, d14, d15, d16, d17 led, radial, t1-3/4, 0.1-in. ls, red 33 1 js1 header, 1x13, 0.1-in. centers, locking 34 1 r19 pot, 50k ? 35 1 u3 fluorescent disp, samsung svv-10ms08 36 1 u4 fluorescent disp, samsung svv-07ms08 37 1 js7 header, 1x4, 0.1-in. centers, jst xhp-4 38 1 js5 header, 1x6, 0.1-in. centers, jst xhp-6 table 45 vfd bill of materials (continued) item qty location description
108 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix h: vfd gerber files preliminary appendix h: vfd gerber files figure 71 vfd control panel top layer
ess technology, inc. sam0400-103101 109 es6008/18/28/38 data sheet appendix h: vfd gerber files preliminary figure 72 vfd control panel bottom layer
110 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix h: vfd gerber files preliminary figure 73 vfd control panel drill template
ess technology, inc. sam0400-103101 111 es6008/18/28/38 data sheet appendix h: vfd gerber files preliminary figure 74 vfd control panel solder mask bottom layer
112 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix h: vfd gerber files preliminary figure 75 vfd control panel solder mask top layer
ess technology, inc. sam0400-103101 113 es6008/18/28/38 data sheet appendix h: vfd gerber files preliminary figure 76 vfd control panel solder paste layer
114 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix h: vfd gerber files preliminary figure 77 vfd control panel silkscreen layer
ess technology, inc. sam0400-103101 115 es6008/18/28/38 data sheet appendix i: vfd control panel schematics preliminary appendix i: vfd control panel schematics figure 78 vfd preamp mic 1 mic 2 key control cw cw cw (volume control, vrs) (echo control, vr) stereo_mic out mic_mix out key_control out open lpf2out vol1out vol2out echovolin vol2in mic1in mic2in mic1in vol1in mic2in vol2in vol1in vol1out vol2out mic_mix mic_mix keydown keyup vocal_on agnd agnd agnd agnd +5v +5v agnd agnd agnd agnd +5va agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd +5va +5va agnd r2 22k r27 470k j3 mini phonejack r25 100k r4 10k r3 2.2k r24 100k + c24 4.7uf + c1 4.7uf r11 vr 50k + c16 4.7uf r12 vr 50k r17 2.2k r19 (vr 50k) + c2 47uf r5 220 r8 10k r6 12k c5 150pf c13 150pf c19 1000pf r13 12k c20 1000pf r15 220 + c17 47uf + c4 1uf + c15 1uf js4 hdr3 lock 1 2 3 d2 1n4148 d1 1n4148 + c10 1uf + c12 1uf + c3 1uf + c18 1uf r9 22k w1 jumper r10 22k r16 47 q1 2n7002lt1 c8 0.1uf q2 2n7002lt1 + c23 10uf c9 0.1uf c11 0.1uf d3 1n4148 d4 1n4148 + c7 47uf + c22 10uf w2 jumper r1 47 + c14 22uf + - - + - . mic1 mic2 mix + u1 ba7760f 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r7 10 r22 5.6k js2 hdr4 lock 1 2 3 4 js3 hdr4 lock 1 2 3 4 + c21 4.7uf u2a 14069 1 2 + c6 10uf u2b 14069 3 4 r26 22k u2c 14069 5 6 r23 1k u2d 14069 9 8 r20 51k r21 51k j1 0.25" phonejack r14 10k j2 0.25" phonejack r18 22k
116 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet appendix i: vfd control panel schematics preliminary figure 79 vfd control panel switching interface vfd power vfd switchs_in g7 vfd 2.54mm spaci ng/0.7mm pin led_out/c2-b siodi vfd_cs sioclk remcon sioclk siodout g1 g2 g3 g4 g5 g6 g7 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 ntsc/pal f2 p16 led1 sw3 sw1 led3 sw4 p14 siodout sw1 siodi p13 p15 led4 -25v led5 p17 vfd_cs led2 sw2 sw4 g10 g9 g8 g7 g6 g5 g4 g1 g3 g2 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 g9 g10 g8 ntsc/pal f1 led1 led4 led5 led2 led3 key1 key2 key3 key4 sk1 sk2 sk3 sk4 sk5 sk6 g6 g4 g1 g2 g5 g3 p12 p15 p16 p11 p14 p7 p13 p10 p9 p8 p12 p11 key3 key1 key2 key4 g5 g3 p9 p6 p7 sk1 p10 p9 p2 sk6 f2 f2 g6 f1 p6 g6 sk3 g4 p5 f2 p2 p4 p8 g2 g3 p1 sk2 p3 sk5 g7 g4 p1 g1 p8 p7 p3 g9 sk4 g2 f1 f1 g1 g8 p5 p4 g5 g11 keydown keyup vocal_on sk_3 sk_2 key_3 sk_6 key_1 sk_1 sk_5 key_4 key_2 sk_4 sioclk_b vfd_cs siodout siodi sw_1 led1 led2 led3 led4 f_2 f_1 p_7 p_8 p_9 p_10 p_11 p_12 p_13 p_14 p_15 p_16 g_1 g_2 g_3 g_4 g_5 g_6 +5v +5v +5v +5v +5v +5v +5v +5v -25v +5v +5v -25v u11 zec vfd20-1301 1 2 53 54 50 49 48 47 46 45 44 43 42 41 40 12 13 14 15 17 16 38 37 36 39 11 10 9 8 7 6 5 f1a f1b f2a f2b 1p 2p 3p 4p 5p 6p 7p 8p 9p 10p 11p 6g 5g 4g 3g 1g 2g 13p 14p 15p 12p 7g 8g 9g 10g 11g 12g 13g r35 4.7k u4 svv-07ms08 1 2 42 43 5 6 7 8 9 10 11 12 13 14 15 34 35 36 37 39 38 17 18 19 20 16 33 f1a f1b f2a f2b 1p 2p 3p 4p 5p 6p 7p 8p 9p 10p 11p 6g 5g 4g 3g 1g 2g 13p 14p 15p 16p 12p 7g r31 10k js5 hdr6 lock 1 2 3 4 5 6 js8 hdr8 lock 1 2 3 4 5 6 7 8 u6 nec16311 22 23 21 20 19 18 17 15 14 13 12 24 25 26 33 27 28 29 30 39 40 11 10 9 8 7 6 5 4 3 2 1 41 42 43 44 45 47 48 49 50 51 52 31 32 34 46 35 36 37 38 s8k8 s9k9 s7k7 s6k6 s5k5 s4k4 s3k3 s2k2 s1k1 vdd key4 key3 s10k10 s11k11 s12k12 vdd s13g16 s14g15 s15g14 s16g13 g6 g5 key2 key1 stb clk ic din dout sw4 sw3 sw2 sw1 g4 g3 g2 g1 vdd led4 led3 led2 led1 vss osc s17g12 s18g11 vee led5 s19g10 s20g9 g8 g7 s25 sw pb u5 vfd28-0704 1 2 34 35 4 5 6 7 8 9 10 11 12 13 14 27 28 29 30 32 31 16 17 18 19 15 20 26 f1a f1b f2a f2b 1p 2p 3p 4p 5p 6p 7p 8p 9p 10p 11p 6g 5g 4g 3g 1g 2g 13p 14p 15p 16p 12p 17p 7g s4 sw pb k1s4 key-resume s10 sw pb k2s4 surround s26 sw pb s8 sw pb k2s2 shuffle r29 10k s21 sw pb k4s3 resume u3 svv-10ms08 1 2 34 35 6 7 8 9 10 11 12 13 14 27 28 29 30 22 31 26 23 24 25 f1a f1b f2a f2b 1p 2p 3p 4p 5p 6p 7p 8p 9p 10p 6g 7g 8g 9g 1g 10g 5g 2g 3g 4g s9 sw pb k2s3 repeat r39 4.7k s7 sw pb k2s1 eject s12 sw pb k2s6 echo + s11 sw pb k2s5 echo - d10 1n4148 s16 sw pb k3s4 slow s18 sw pb k3s6 ff s24 sw pb k4s6 prev s17 sw pb k3s5 fr s28 sw pb s33 ntsc/pal r32 56k c25 0.1uf r38 4.7k c28 0.1uf jp1 hdr 2 1 2 s23 sw pb k4s5 next s2 sw pb k1s2 pbc c30 0.1uf + c29 47uf 35v u2f 14069 13 12 c27 0.1uf r40 4.7k u2e 14069 11 10 js6 hdr4 lock 1 2 3 4 js7 hdr4 lock 1 2 3 4 s22 sw pb k4s4 x s19 sw pb k4s1 stop d8 1n4148 s13 sw pb k3s1 play r43 4.7k s1 sw pb k1s1 power d6 1n4148 s14 sw pb k3s2 pause d7 1n4148 d5 1n4148 s15 sw pb k3s3 vocal-assist u7 tfms5380 1 2 3 d9 1n4148 s27 sw pb s5 sw pb k1s5 key - s3 sw pb k1s3 mode s6 sw pb k1s6 key + d11 1n4148 + c26 47uf r36 4.7k r28 10k r30 10k s20 sw pb k4s2 x g10 g11 p17 p16 p10 p15 p14 p13 p12 p11
ess technology, inc. sam0400-103101 117 es6008/18/28/38 data sheet appendix i: vfd control panel schematics preliminary figure 80 vfd controller interface vfd 2.54mm spaci ng/0.7mm pin f1 f2 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 f1 p15 f2 p16 g6 g5 g4 g3 g2 g1 led4 led3 led2 led1 led4 led3 led2 led1 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 sw4 p16 sw3 sw2 sw1 g6 g5 g4 g3 g1 g2 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 g1 g2 g3 g4 g5 g6 led4 led3 led2 led1 key_1 key_2 key_3 key_4 sk_1 sk_2 sk_3 sk_4 sk_5 sk_6 f_2 f_1 siodout siodi vfd_cs sioclk_b keyup keydown vocal_on sw_1 g_1 g_2 g_3 g_4 g_5 g_6 p_7 p_8 p_9 p_10 p_11 p_12 p_14 p_13 p_15 p_16 +5v +5v -25v u8 vfd6-bt-267gk 1 2 34 35 19 18 17 16 15 14 13 12 11 10 9 32 31 30 29 27 28 7 6 5 4 8 f1a f1b f2a f2b 1p 2p 3p 4p 5p 6p 7p 8p 9p 10p 11p 6g 5g 4g 3g 1g 2g 13p 14p 15p 16p 12p c33 open r44 51k c31 0.1uf + c32 47uf u10 nec16312 22 23 21 20 19 18 17 16 15 14 13 12 24 25 26 27 28 29 30 31 32 33 11 10 9 8 7 6 5 4 3 2 1 34 35 36 37 38 39 40 41 42 43 44 seg8 seg9 seg7 seg6/ks6 seg5/ks5 seg4/ks4 seg3/ks3 seg2/ks2 seg1/ks1 vdd key4 key3 seg10 seg11 seg12/g11 vee seg13/g10 seg14/g9 seg15/g8 seg16/g7 g6 g5 key2 key1 stb clk vss din dout sw4 sw3 sw2 sw1 g4 g3 g2 g1 vdd led4 led3 led2 led1 vss osc c34 0.1uf u9 vfd6-bt-297gk 1 2 34 35 12 13 14 15 18 19 20 21 24 25 26 4 5 6 7 10 9 29 30 31 32 27 f1a f1b f2a f2b 1p 2p 3p 4p 5p 6p 7p 8p 9p 10p 11p 6g 5g 4g 3g 1g 2g 13p 14p 15p 16p 12p
118 sam0400-103101 ess technology, inc. es6008/18/28/38 data sheet mechanical dimensions preliminary mechanical dimensions figure 81 208-pin plastic quad flat package (pqfp) see detail a e e1 152 157 208 index 53 104 d d1 105 pin 1 note: 1. all dimensions are in millimeters. 2. actual package uses millimeter native dimensions ? care should be taken when converting from metric to imperial. symbol min nom max a 3.42 3.70 4.09 a1 0.25 0.33 0.42 a2 3.17 3.37 3.67 b 0.13 0.17 0.27 d 30.35 30.60 30.85 d1 27.90 28.00 28.10 e 0.0197 (0.50) basic e1 0.20 basic e 30.35 30.60 30.85 e1 27.90 28.00 28.10 l0.35 ? 0.75 l1 ? 1.30 ? 0 ? 7 e a1 a2 l b 156 e1 l1
ess technology, inc. sam0400-103101 119 es6008/18/28/38 data sheet preliminary
120 ? 2001 ess technology, inc. sam0400-103101 es6008/18/28/38 data sheet ordering information preliminary no part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ess technology, inc. ess technology, inc. makes no representations or warranties regarding the content of this document. all specifications are subject to change without prior notice. ess technology, inc. assumes no responsibility for any errors contained herein. (p) u.s. patent 4,214,125 and others, other patents pending. mpeg is the moving picture experts group of the iso/iec. references to mpeg in this document refer to the iso/iec jtc1 sc29 committee draft iso 11172 dated january 9, 1992. video drive ? is a trademark of ess technology, inc. dolby is a trademark of dolby laboratories, inc. h.261 refers to the international standard described in recommendation h.261 of the ccitt working party 15-1. all other trademarks are trademarks of their respective companies and are used for identification purposes only. all other trademarks are owned by their respective holders and are used for identification purposes only. ordering information part number description package es6008f 2-channel dvd and tv encoder 208-pin pqfp ES6018f 6-channel dvd, dts and tv encoder 208-pin pqfp es6028f 6-channel dvd, dts, progressive scan and tv encoder 208-pin pqfp es6038f 6-channel dvd, dts, progressive scan, dvd-audio and tv encoder 208-pin pqfp

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